bearing wrote:The powerstage and motor can simply be simulated as a pulsed current when playing with capacitor values. It doesn't matter if the motor current has some slope to it.
The ceramic/film capacitors are only there to take care of the flanks. They need to have low ESL. The electrolytics take care of the main current. To be able to simulate what's going on during the flanks you need to model: the electrolytics ESL+ESR, stray inductance between the electrolytics and the ceramic/film, and stray inductance between ceramics and power stage.
bearing wrote:Regarding your cocksure answers to rhitee05 earlier, I would like to know on what science you are basing your answers? to me it seems like rhitee05 has got it all right, which makes you the one who needs to explain your sources and reasoning.
Teh Stork wrote:This document:[url=http://www.ecicaps.com/pdf/whitepapers/IEMDC_2009_11310_Final_Rev_4.pdf]Selecting Film Bus Link Capacitors
For High Performance Inverter Applications[/url]
Why won't it link :S - Selecting Film Bus Link Capacitors
For High Performance Inverter Applications: from Epicaps
Maybe you should start here:
That article is fatally flawed and very, very wrong.
Motor inductance still doesn't matter for capacitor sizing...
one prototype is worth 1000 simulations
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