Lebowski's motor controller IC, schematic and setup manual

[deVries]

We had a rainy weekend here with unpredictable weather, so lots of time to work on the PCB.

Only one sunny day allowed per week, well, until the kit arrives.

May it rain rain rain...

[nieles]

Got my controller working again! i replaced the driver chip, and it works like before!

now the "bad" news, i definitely need to add some snubbers!

this is the high side gate signal

h_a_gate1.jpg (17.71 KiB) Viewed 213 times

h_a_gate.jpg (18.46 KiB) Viewed 213 times

h_a_gate2.jpg (21.02 KiB) Viewed 213 times

this is the phase a to gnd signal going to the motor

h_a_source.jpg (17.79 KiB) Viewed 213 times

h_a_sourc1.jpg (22.29 KiB) Viewed 213 times

and the low side gate signal. not sure what is going on here?

l_a_gate.jpg (17.96 KiB) Viewed 213 times

[Lebowski]

The snubber are between the drain and source.
To chose snubber component values I follow the following cookbook:

- As you can see in your picturs, there's ringing on the drain/source voltage of the FET. Measure the frequency of the ringing.
- Experiment by placing different values of capacitors across the drain / source. Determine the capacitor value for which the
frequency of the ringing is about half to one-third of the original ringing frequecy. This gives you the capacitor value for
the snubber. For a 4115 I found 3.3 to 4.7 nF a good fit (depends on battery voltage, more voltage -> lower cap).
- calculate the impedance of the capacitor at the new (lower) ringing frequecy using X = 1 / (2 * pi * f_new_ring * C_snub)
- the snubber resistor should be taken as 1.5 times the capacitor impedance X.

Now the only thing to watch out for is the power dissipated in the snubber resistor. This is given by:

P_snub_r = f_pwm * C_snub * (V_bat)^2

First put snubbers between all drain/sources of the FET's (see also attached picture where the snubbers are the 4.7 nF and 6.8 Ohm components)

After this is done, look at the gate / source signals. Chose the gate resistors such that there's no significant overshoot which can
blow the gate oxide. Im my controller I didn't need gate resistors, the gate signals looked nice and clean after snubbing the drain/source's.
If the drain/sources are not snubbed the ringing will 'transfer' to the gate by means of the Cgd, this is what you're seeing.

sine_controller-output_stage_B.jpg

(127.91 KiB) Downloaded 3 times

[nieles]

i have 10 ohm gate resistors in place.

i also have a 10k (or 20k) and a 15v (or 17v) zener diode beteween the gate and source of each fet.

i have ordered some 1nf 2.2nf and 4.7nf capacitors along with a few 100 low value 0.25w resistors to make a snubber.

Thanks for posting the calculations again. i have them written down somewhere, but this saves me a few hours of searching

Will post again when i have some progress.

can i damage something by only snubbing one phase first? i would think this is not a problem but i am not 100% sure

[Lebowski]

i have 10 ohm gate resistors in place.

i also have a 10k (or 20k) and a 15v (or 17v) zener diode beteween the gate and source of each fet.

i have ordered some 1nf 2.2nf and 4.7nf capacitors along with a few 100 low value 0.25w resistors to make a snubber.

Thanks for posting the calculations again. i have them written down somewhere, but this saves me a few hours of searching

Will post again when i have some progress.

can i damage something by only snubbing one phase first? i would think this is not a problem but i am not 100% sure

I snubbed one phase first too, I used the 'generate test signal' from the PWM menu when I chose the snubber values.
Just don't put any power through the output stage before it's snubbed. When you use the 'generate test signal' option
all 3 PWM channels move in sync, so no effective voltage is put accross the motor. I did not have my motor connected
when I chose the snubber values. Very important is to have a 0.47 uF high voltage cap on the battery supply. Put this cap
as close as possible to the power FETs but inbetween the FET's and the battery. The job of this cap is to shorten
the (to be snubbed) inductive loop.

Make sure that the snubber caps have the correct voltage rating ! (must be higher than the battery voltage)

[nieles]

i have 8 of these beteween V+ and gnd. close to the fets
http://www.ebay.nl/itm/470nF-100V-Phili ... 1c1afc3ca3

so i should be okay there!

the capacitors i have for the snubbers are these:
http://www.ebay.nl/itm/20-Polyester-Pol ... 1242wt_794

[Arlo1]

Niles would you not be able to reduce the ringing by reducing the voltage you are applying to the fet gates?

[nieles]

not 100% sure what you mean, but i am only using 12v supply for the gates, going lower will not fully turn the fets on.

[Arlo1]

not 100% sure what you mean, but i am only using 12v supply for the gates, going lower will not fully turn the fets on.

Are you using 4115 fets?
Looks like a 9 volt supply would be OK. I think it was bigmoose who pointed out to me you want to be just above the miller plateau.
Post edited:

[Lebowski]

I use 17V for the gate drive. The nasty bit in the whole curve is the miller plateau, while
the FET is in there it's dissipating power (because it's already conducting and has
a large voltage across it). To get through the plateau quickly you need a lot of 'overvoltage'
above the plateau. So, 17V gives you 10 V overvoltage (10V above the 7V plateau) meaning
that the gate current will be 10V / whatever resistance your gate driver is (typically
5 to 7 Ohm for a NCP 5181).

My FET's are on in 0.2 usec.

[Lebowski]

Niles would you not be able to reduce the ringing by reducing the voltage you are applying to the fet gates?

It is all proportional, ringing is proportional in amplitude to the gate voltage.

[Teh Stork]

Too long deadtime and too much stray inductance. The ringing is set off by the body diode being shut down. What fets are you using Nieles?

[Lebowski]

Too long deadtime and too much stray inductance. The ringing is set off by the body diode being shut down. What fets are you using Nieles?

I don't agree with this.

[Teh Stork]

Too long deadtime and too much stray inductance. The ringing is set off by the body diode being shut down. What fets are you using Nieles?

I don't agree with this.

Look to this topic for a detailed breakdown of the phenomenon: linksy.

[Lebowski]

Too long deadtime and too much stray inductance. The ringing is set off by the body diode being shut down. What fets are you using Nieles?

I don't agree with this.

Look to this topic for a detailed breakdown of the phenomenon: linksy.

I don't agree with that entire thread either

[Arlo1]

We should get bigmoose to chime in but i think snubbers are the wrong way to bandaid fix this. Is it not better to tune the fet ringing out with the proper voltage/ gate resistor combination?

[Lebowski]

We should get bigmoose to chime in but i think snubbers are the wrong way to bandaid fix this. Is it not better to tune the fet ringing out with the proper voltage/ gate resistor combination?

this would mean making the transitions on the gate very slow, slowing down the whole
switching behavior and burning more power in the FETs. Zombiess showed in his
thread that the typical china controller has very weak gate drivers and 'survives' without
snubbers by being slow.

[Jeremy Harris]

Snubbers are a bit of a band aid, as if the stray inductance can be kept low then the chances are they won't be needed. The point about transition speed is a good one, and certainly the microsecond switching time of a typical Chinese controller helps, but I can say with certainty that you can switch at around 200 to 300 nS and not get spikes or ringing on the FET outputs, IF you ensure that the stray inductance is kept low and that you are rigorous with the placement of good, low ESR, wide bandwidth, commutation capacitors.

I found that a distributed array of capacitors, with a mix of low ESR (but relatively high inductance) electrolytics, together with medium value polypropylene and low value ceramics, placed right next to the FETS, on each pair, worked well at reducing any switching transients, so removing the need for snubbers.

[bigmoose]

Good comments all around. Snubbers are definitely another tool in the tool box. The design method for them is sound. Like said above, use them to cancel layout and parasitic inductance.

Guys remember each designer has a bit of a different style with this. Lebowski has a good design going, and we should all let him roll his optimum out. It is like driving the FETs above the miller plateau, it is about current over time to charge the Q. You can do it with a higher voltage and a high source impedance of the driver, or lower voltage and a low source impedance driver. They will both do the job. I have design rules that won't let me drive a 20V gate to 17 volts due to derating criteria... That does not mean it won't work... just a different optimization, the heart of engineering!

[Arlo1]

Fast switching is good for hi pwm rates and can help to keep controller efficiency up hmmmmm. Who needs school when i got you guys!

[nieles]

added a 2.2nf capacitor beteween S-D,
this is what the signal looks like now:

h_a_s_23_5.jpg (20.78 KiB) Viewed 359 times

tonight i will add the resistors in series with the capacitor.

should i add an other 1nf in parallel to the 2.2nf? or leave it like this.

[Lebowski]

added a 2.2nf capacitor beteween S-D,
this is what the signal looks like now:

h_a_s_23_5.jpg

tonight i will add the resistors in series with the capacitor.

should i add an other 1nf in parallel to the 2.2nf? or leave it like this.

I assume before the 2.2 nF it was 24.5 MHz ? I would just try 2.2, 3.2 and 4.4 and look at the final snubbed waveform and choose what you like best.

With the 2.2 nF and 14.3 MHz the snubber resistors should be roughly 7.6 ohm (8.2, or 2 of 15 in parallel).

For determining snubber values, scope the drain/source voltage, not the gate/source.
Also, the snubber cap decreases with an increase in battery voltage (see the Coss graphs in the FET specs).
Point being, apply close to the final battery voltage when determining snubber values, else you will
larger than necessary snubber caps. Large snubber caps is actually even better for snubbing but it
also increases the power dissipation in the snubber resistor so it's a balancing act (nothing is free in
engineering).
The snubber should be soldered as close as possible to the FET with the shortest possible wires / smallest
inductive loop. DO NOT USE WIRE-WOUND RESISTORS !!! they have too much inductance.

[Teh Stork]

Uhm, I'd like to suggest using "gate resistors" in series with the bootstrap capacitor - if your components allow it. This will allow you to keep the fall time, but it will limit your rise time. The high side transition normally is the problem.

Regarding rise time and ringing frequency; This is a area where I've heard lots of stuff - but not quite managed to separate the BS from the truth. A 14MHz ringing frequency would imply that the pulse that set it off was extremely slim; one period is ~70nSec. The rise time of the fets isn't slim enough to create this. The only culprit I can find is the body diode of the other fet - being shut down. Minority carriers will shut down in a fast and violent way - mosfets are irradiated and added precious metals to give them soft recovery properties - why would they if they didn't need to?

[liveforphysics]

Looks like a 9 volt supply would be OK. I think it was bigmoose who pointed out to me you want to be just about the miller plateau.

You MUST switch above the miller plateau by a healthy amount.

[Arlo1]

Looks like a 9 volt supply would be OK. I think it was bigmoose who pointed out to me you want to be just about the miller plateau.

You MUST switch above the miller plateau by a healthy amount.

Sorry post was suposed to say "above" no about. I will edit now. What is a healthy amount? 10% 50% ?????? Bigmoose pointed out on the robotics controller he diagnosed if they have to hi voltage and or to low gate resistor it will cause ringing!