Lebowski's motor controller IC, schematic and setup manual

[liveforphysics]

Your switching loss won't show up until touching the plateau is actually causing current to flow.

[Lebowski]

Your switching loss won't show up until touching the plateau is actually causing current to flow.

but by that time the dissipative losses in the Rds_on should be much higher than the switching losses, no ?

[liveforphysics]

Your switching loss won't show up until touching the plateau is actually causing current to flow.

but by that time the dissipative losses in the Rds_on should be much higher than the switching losses, no ?

I would hope so, or you're not running it very hard. But this and only this is when the switching loss gets added. Only a tiny tiny percentage of switching loss is actually the act of charging and discharging the gate grid unloaded, it's when you trigger current and it pulls the source up and sends it back into the trans conductance region.

[Lebowski]

Your switching loss won't show up until touching the plateau is actually causing current to flow.

but by that time the dissipative losses in the Rds_on should be much higher than the switching losses, no ?

I would hope so, or you're not running it very hard. But this and only this is when the switching loss gets added. Only a tiny tiny percentage of switching loss is actually the act of charging and discharging the gate grid unloaded, it's when you trigger current and it pulls the source up and sends it back into the trans conductance region.

The dissipation in the FET is massive while in miller plateau so you should go through the plateau as quick as possible... I have a 2 Gs/sec scope with something
like 500 MHz BW and had to zoom in almost to the minimum timescale to see the plateau (which fits, 30 nC of a 4115 can be delivered in 15 nsec with a 2A driver)...

What do you call transconductance region ? isn't the transconductance the gm, like in delta_Id = gm * delta_Vgs ? AFAIK you have the triode region (when the FET
acts as a resistor) and the saturation region (when the FET acts as a controlled current source having a certain transconductance).

[bigmoose]

... it's when you trigger current and it pulls the source up and sends it back into the trans conductance region.

Bingo! I think you would benefit from gate resistors (3 to 4 to 10 ohms) and slowing down your edges, but that is just my opinion.

[nieles]

got around to install two new snubbers, this time a 4,7nf capacitor and 5x33R (6.6R) resistor.

this is what it looks like:

4.7nf and 6.6r snubber (26-050-12)-2 (1).jpg (48.37 KiB) Viewed 229 times

max Voltage: 46v

[Lebowski]

So now you have snubbers on 1 full bridge (2 out of 6 FETs) ? Try to snub all 6, it'll look even better....

[nieles]

yes i noticed that. i have the "old" (2.2nf snubbers) on 1 fet pair, the new snubbers on 1 fet pair, and then one pair not snubbed at all.
i had the scope on the fet pair without snubbers, and it looked a lot better than without any snubbers installed on all phases.

do you have any progress reports from other people working with your controller chip?

[Arlo1]

I have 16hr of customer work to do in the next 24hr then I have a nose surgery (they are going to dill it out so I can breath!) Then I plan to relax and solder a curcuit board or two together end of this week.

I just got some Photo Basic Glossy paper from staples and used a lazerjet printer and printed the file you give me niles. I also have Hydrogerperoxide and Muriatic acid to mix up for etching then I will try to get a couple boards etched on my lunch today so its ready for next week. I also have to KNurl my motorcycle dyno roller today so maybe I can help dynotune my friends motocross bikes for the nationals in town next weekend...... Im trying I realy am!

[Lebowski]

yes i noticed that. i have the "old" (2.2nf snubbers) on 1 fet pair, the new snubbers on 1 fet pair, and then one pair not snubbed at all.
i had the scope on the fet pair without snubbers, and it looked a lot better than without any snubbers installed on all phases.

do you have any progress reports from other people working with your controller chip?

Not really, I sent out 10 but only heard back from you and Arlo I'm making a PCB now to make it easier
for people to use my IC (and because I need a new controller for expanding the controller IC to also include
sensorless power-startup from standstill (like with hall sensors)).

The ringing of an unsnubbed FET-pair propagates to the supply, this is why you see the FET's influencing each other.

Once you've snubbed all FETs across the drain/source, have a look at the gate-source waveform of a low-side FET.
In my case these were all nice and clean square waves, I'm curious to see what yours look like. If you've got any ringing
or overshoot there, this can be snubbed with a gate-resistor.... Note that the NCP5181 already has a few ohms internal
resistance in the line to the gate, in my case this was already enough gate resistance.

[liveforphysics]

I've got your chip sitting right in the middle of my workshop bench.

As soon as I finish up the half dozen projects ahead of it, I'm diving in.


Remember, this ringing isn't from the RC circuit between the gate and drive resistance and inductance.
The ringing is from source reference dipping the moment it starts to conduct, and this dip taking the gate out of the conductive area, then source voltage slams back up because its not conducting any more, which in turn re-biases the gate and: t conducts again, repeat repeat repeat. Because of source dipping as it conducted, it also makes the pleteau very obvious and bouncy. Trying to tune the gate circuit with no load on the FET is like trying to tune your cars suspension with the wheels off the ground.

[nieles]

what kind of capacitance is needed right at the drain-source of controllers? i have one 0.47uf mkt cap per fet, fairly close to the fet. (0.5-1cm away)
or is the esr of the caps more important than the capacitance?


i also have 3 of these:
http://www.icel.it/pdf/26_PMB.pdf
i have the 1uf 1200v versions.
but i have no way to connect them on my controller how i have configured it now.

[Lebowski]

I so don`t agree with you Luke
Ringing is based on basic LRC circuitry with the L coming from wiring inductance and the C coming from Coss or Ciss (dependent on whether you`re looking at drain-source or gate-source). If you look at a simple series circuit of a voltage source, L and C you will get ringing over the C when you generate a voltage step with the voltage souce. In my 4115 controller, the L is 94nH, the C 1 nF (which is the value of Coss for a 4115 at 60 V). You can simulate this circuit in LTSpice. Now to add the snubber in this you put the series RC in parallel with the 1 nF C. For the RC take 4.7 nF and 7.2 Ohm. Simulate again with a voltage step in the voltage source. This will show the damped waveform you get with a snubber.

Instead of an RC circuit in parallel to the drain-source it would be better to only have the R in series with the drain-source but this is not possible as it would limit motor current.That`s why a bigger, more dominant C is added in parallel, with a R in series (the RC snubber). For the gate side of the FET a resistor in series with the L(wiring inductance) and C(FET input capacitance) is no problem, therefore a gate resistor can be used to dampen the LC tank.

Note by the way, a typical 470nF cap, used across the battery wirew close to the FETs to limit the inductance, is an LC series circuit by itself with a resonance freq of 2 to 3 MHz (if I remember correctly). So there is an L in there too !

Going back to the RLC circuit of the drain-souce side: the ringing is kicked off by 2 things. First is the voltage jump across Coss, this cap needs to be charged with .5*C*V^2. The second kick is the phase current that was running through part of the wiring L (NOT the motor L), the energy behind this kick is .5*L*I^2. This second kick is added when there`s phase current flowing but the first kick of the capacitor is always there !


man it`s hard to type on a Nibrendo 3DS

[liveforphysics]

First, props for typing on a Nintendo.

Second, I used to think this same thing. I learned I was mistaken when I made my big FET array for testing the A123 pouches. My gate waveform looked beautiful before it was under high current loading. The moment it was under load, it bounced all over hell and back, ringing the FETs a few dozen times for each switching cycle, and as I slid the welding clamp around on my bar of stainless serving as my variable load resistor, I could directly watch the amplitude, quantity of bounces, and duration of time it spent bouncing around increase in perfect sync with my load resistor decreasing resistance.

Going from 5ohm gate resistors to 22ohm gate resistors slowed the dI/dT slew rate of the FET conducting, which reduced the spikes by a huge amount, reducing the overall time the FETs were in the trans-conductance zone and the heat the FETs made by a huge amount. However, the 22ohm gate resistors made the switching look much slower and longer when the circuit was NOT under load. Lucky for my circuit, its goal wasn't to win an unloaded scope image waveform beauty contest, it was to function under load, and just adding 4x the gate resistance enabled it to work.

[Teh Stork]

I have to support Luke here, this is exactly the same as my observations.

When I started testing my controller with a inductive load I found the whole thing bursting into oscillations, triggering UVLO in the gate drivers, reset in my AVR and my labsupply's current limiting. The EM noise was insane xD. The solution was first the same thing as Luke did - increase the gate resistors. Later on I read up on body diode recovery times and the deadtime optimalizations you can do there. Note that datasheets often show their recovery times at redicolous dI/dT times. Like 200A/uS - when you, with 100A and 100ns will be switching 1000A/uS. I'm working on a predictive gate driver that will handle some proper gate charge - unlike TI's predictive gate drivers witch is limited at 50nC (Datasheet says 120nC - but it wont work properly with this much). Read up on a app-note on a buck converter witch employs synchronous rectification, and spesifically on the part of the deadtime insertion - three phase inverters are basically three phase buck converters.

Snubbers will help against dV/dT induced turn on, but not with the many problems regarding the body diode (dI/dT).

[Arlo1]

made some progress today. Started a diy circuit board thread here viewtopic.php?f=1&t=40183 because i would like to perfect my skills and help others see how easy it is.

[nieles]

lebowski,

i am doing some tests to get my controller running with the 6374 brushless motor smooth, and without cutting out to drive_0. i am experimenting with different values for Menu E option b,c and d. and also with different values for the IIR filter.

could you explain a little more about what the filter does, and what the effects are by changing to a higher or lower value (between 2 and

[Lebowski]

First, props for typing on a Nintendo.

Second, I used to think this same thing. I learned I was mistaken when I made my big FET array for testing the A123 pouches. My gate waveform looked beautiful before it was under high current loading. The moment it was under load, it bounced all over hell and back, ringing the FETs a few dozen times for each switching cycle, and as I slid the welding clamp around on my bar of stainless serving as my variable load resistor, I could directly watch the amplitude, quantity of bounces, and duration of time it spent bouncing around increase in perfect sync with my load resistor decreasing resistance.

Going from 5ohm gate resistors to 22ohm gate resistors slowed the dI/dT slew rate of the FET conducting, which reduced the spikes by a huge amount, reducing the overall time the FETs were in the trans-conductance zone and the heat the FETs made by a huge amount. However, the 22ohm gate resistors made the switching look much slower and longer when the circuit was NOT under load. Lucky for my circuit, its goal wasn't to win an unloaded scope image waveform beauty contest, it was to function under load, and just adding 4x the gate resistance enabled it to work.

I wish i had access to the setup you're talking about, I bet somewhere in there you would find an LC oscillator in the small signal equivalent circuit.
I'll process the PCB as I am designing it now. I will order 2, one for my own development and one for a high power version (150V components
and 150A current sensors). I have this ME602 which I can use as a load, I'll put 50 A though it to see what happens with the FET driver
circuitry. First order of business though is to finish my big Digikey order for parts, then measure all the legs to make sure I got the
drill sizes for the PCB correct.
I still think though that gate resistors should only be used to dampen the ringing of the gate RLC, not to fix issues at the drian/source side.
But let's see what the static experiments with the ME602 show....

[Lebowski]

lebowski,

i am doing some tests to get my controller running with the 6374 brushless motor smooth, and without cutting out to drive_0. i am experimenting with different values for Menu E option b,c and d. and also with different values for the IIR filter.

could you explain a little more about what the filter does, and what the effects are by changing to a higher or lower value (between 2 and 8 )

Did you try following the calculations in the manual ? For my bike I followed them to the letter using y=256 and a 1 msec LR delay time.
The filter should definately be more towards 8 than 2, I use 7 myself. I never had a cut-out to drive 0 with this setup (and I've done 150 km now).
Also don't make menu d options f and g too small (shutdown error current levels), I have them both set at 2 A with a max phase amps of 16.

The way it works is that in order to detect a fault the algorithm compares the measured with the expected motor currents. When the difference
is larger than Menu D, options f and g it cuts out to drive 0. Now because we're dealing with noisy current sensors in a high power switchin environment,
some amount of filtering is necessary 'cause else it would cut out all the time. This is what the comb filter and the filter does, they filter the measured
error current before it is compared with the cutout levels, to prevent accidental cutout due to a spike on the current sensor outputs.

The options for the control loops (menu E, options b,c and d) also have an impact. The control loops operate on the same noisy info from the
current sensors. Because of the noise the control loops can occasionally be send in the wrong direction. normally it will detect this and recover.
But if menu E, options b,c and d are chosen incorrectly the step in the wrong direction can be so big that the subsequent current measurements
are way off, tripping the current cutout levels.

I noticed that for kind of randomly chosen values for options b,c and d you can really mess it up and have it cut out to drive 0 all the time.
Drive 0 is meant only for power up and after something seriously went wrong, normally you should never see this mode.

[nieles]

Did you try following the calculations in the manual ? For my bike I followed them to the letter using y=256 and a 1 msec LR delay time.The filter should definately be more towards 8 than 2, I use 7 myself. I never had a cut-out to drive 0 with this setup (and I've done 150 km now).Also don't make menu d options f and g too small (shutdown error current levels), I have them both set at 2 A with a max phase amps of 16.

yes, i used the formulas given in the manual.

i am using y:1024 and an lr delay of 2ms(will be lowering this after each test) IIR filter set to 6.

[Arlo1]

Ok so I started to build up on of my ok boards I copied from Neile's today. And after that I worked on my prototyping board and found its still a PITA to get into the set up mode but what I did find is the usb-serial adapter looks like the problem it flashes the light relay dimly and wont work but once i get the chip into setup mode it flashes the light brightly and the terminal program responds properly. So I will finish Nieles board soon and try it with the transistors instead of the max232 chip that is on the protoboard. But i'm sure its my usb-serial adapter that's giving me problems now I did update the driver recently but I think its something in the driver or settings that wont let it wake up when I need.

As for the pic30f4011 getting warm on the protoboard its not bad just probably 40deg C so IM not sure if I need to worry about that.
I would really like to get the protoboard working properly but I'm on my only usb-serial cable and I hate to buy another one and have it cause issues as well.
I'm using windows 7 and I found on the altrax website they have seen issues with usb-serial adapters only a couple work with windows 7 and their controllers.

[MitchJi]

Hi,

I used to think this same thing. I learned I was mistaken when I made my big FET array for testing the A123 pouches. My gate waveform looked beautiful before it was under high current loading. The moment it was under load, it bounced all over hell and back, ringing the FETs a few dozen times for each switching cycle, and as I slid the welding clamp around on my bar of stainless serving as my variable load resistor, I could directly watch the amplitude, quantity of bounces, and duration of time it spent bouncing around increase in perfect sync with my load resistor decreasing resistance.

I wish i had access to the setup you're talking about, I bet somewhere in there you would find an LC oscillator in the small signal equivalent circuit.

I'll process the PCB as I am designing it now. I will order 2, one for my own development and one for a high power version (150V components and 150A current sensors)...

I still think though that gate resistors should only be used to dampen the ringing of the gate RLC, not to fix issues at the drian/source side. But let's see what the static experiments with the ME602 show....

I've got your chip sitting right in the middle of my workshop bench.

As soon as I finish up the half dozen projects ahead of it, I'm diving in.

When you dive in can you easily assemble a set up, preferably one that Lebowski can easily duplicate or verify, that resolves this discussion (one way or the other)?

[nieles]

when my new driver chips show up, i will try a 50ohm gate resistor and then gradually lower it until the spikes become too high.
what would be a safe time period until the miller plateau? i think i read somewhere bigmoose liked to have about 1us switch on/off times.

hopefully this will stop ruining my driver chips

[Teh Stork]

when my new driver chips show up, i will try a 50ohm gate resistor and then gradually lower it until the spikes become too high.
what would be a safe time period until the miller plateau? i think i read somewhere bigmoose liked to have about 1us switch on/off times.

hopefully this will stop ruining my driver chips

1us switch on/off switch times says little about the actual switching time. If you use 100ns or 200ns at the miller plateau could be all the difference in the world.

My driver chips came "thermally enhanced". After redesigning my pcb i added ground planes under them to cool off better - and the temperature of the drivers definitely dropped.

Look at what shane colton has written about the topic, he's built quite a few awesome controllers

[Arlo1]

Ok so I built up a board like Nieles and no luck I have tried 3 usb to serial adapters! I am going to try a old computer tonight and I also have a usb-serial adapter comming that nieles recomended! With the FTDI chip and Hopefully that will work. So frustrating. I need to simply get the computer to comunicate with the dspic chip but the serial adapter will not wake up I have wasted a lot of time for this very little step