Lebowski's motor controller IC, schematic and setup manual

[Lebowski]

Niles would you not be able to reduce the ringing by reducing the voltage you are applying to the fet gates?

It is all proportional, ringing is proportional in amplitude to the gate voltage.

[Teh Stork]

Too long deadtime and too much stray inductance. The ringing is set off by the body diode being shut down. What fets are you using Nieles?

[Lebowski]

Too long deadtime and too much stray inductance. The ringing is set off by the body diode being shut down. What fets are you using Nieles?

I don't agree with this.

[Teh Stork]

Too long deadtime and too much stray inductance. The ringing is set off by the body diode being shut down. What fets are you using Nieles?

I don't agree with this.

Look to this topic for a detailed breakdown of the phenomenon: linksy.

[Lebowski]

Too long deadtime and too much stray inductance. The ringing is set off by the body diode being shut down. What fets are you using Nieles?

I don't agree with this.

Look to this topic for a detailed breakdown of the phenomenon: linksy.

I don't agree with that entire thread either

[Arlo1]

We should get bigmoose to chime in but i think snubbers are the wrong way to bandaid fix this. Is it not better to tune the fet ringing out with the proper voltage/ gate resistor combination?

[Lebowski]

We should get bigmoose to chime in but i think snubbers are the wrong way to bandaid fix this. Is it not better to tune the fet ringing out with the proper voltage/ gate resistor combination?

this would mean making the transitions on the gate very slow, slowing down the whole
switching behavior and burning more power in the FETs. Zombiess showed in his
thread that the typical china controller has very weak gate drivers and 'survives' without
snubbers by being slow.

[Jeremy Harris]

Snubbers are a bit of a band aid, as if the stray inductance can be kept low then the chances are they won't be needed. The point about transition speed is a good one, and certainly the microsecond switching time of a typical Chinese controller helps, but I can say with certainty that you can switch at around 200 to 300 nS and not get spikes or ringing on the FET outputs, IF you ensure that the stray inductance is kept low and that you are rigorous with the placement of good, low ESR, wide bandwidth, commutation capacitors.

I found that a distributed array of capacitors, with a mix of low ESR (but relatively high inductance) electrolytics, together with medium value polypropylene and low value ceramics, placed right next to the FETS, on each pair, worked well at reducing any switching transients, so removing the need for snubbers.

[bigmoose]

Good comments all around. Snubbers are definitely another tool in the tool box. The design method for them is sound. Like said above, use them to cancel layout and parasitic inductance.

Guys remember each designer has a bit of a different style with this. Lebowski has a good design going, and we should all let him roll his optimum out. It is like driving the FETs above the miller plateau, it is about current over time to charge the Q. You can do it with a higher voltage and a high source impedance of the driver, or lower voltage and a low source impedance driver. They will both do the job. I have design rules that won't let me drive a 20V gate to 17 volts due to derating criteria... That does not mean it won't work... just a different optimization, the heart of engineering!

[Arlo1]

Fast switching is good for hi pwm rates and can help to keep controller efficiency up hmmmmm. Who needs school when i got you guys!

[nieles]

added a 2.2nf capacitor beteween S-D,
this is what the signal looks like now:

h_a_s_23_5.jpg (20.78 KiB) Viewed 364 times

tonight i will add the resistors in series with the capacitor.

should i add an other 1nf in parallel to the 2.2nf? or leave it like this.

[Lebowski]

added a 2.2nf capacitor beteween S-D,
this is what the signal looks like now:

h_a_s_23_5.jpg

tonight i will add the resistors in series with the capacitor.

should i add an other 1nf in parallel to the 2.2nf? or leave it like this.

I assume before the 2.2 nF it was 24.5 MHz ? I would just try 2.2, 3.2 and 4.4 and look at the final snubbed waveform and choose what you like best.

With the 2.2 nF and 14.3 MHz the snubber resistors should be roughly 7.6 ohm (8.2, or 2 of 15 in parallel).

For determining snubber values, scope the drain/source voltage, not the gate/source.
Also, the snubber cap decreases with an increase in battery voltage (see the Coss graphs in the FET specs).
Point being, apply close to the final battery voltage when determining snubber values, else you will
larger than necessary snubber caps. Large snubber caps is actually even better for snubbing but it
also increases the power dissipation in the snubber resistor so it's a balancing act (nothing is free in
engineering).
The snubber should be soldered as close as possible to the FET with the shortest possible wires / smallest
inductive loop. DO NOT USE WIRE-WOUND RESISTORS !!! they have too much inductance.

[Teh Stork]

Uhm, I'd like to suggest using "gate resistors" in series with the bootstrap capacitor - if your components allow it. This will allow you to keep the fall time, but it will limit your rise time. The high side transition normally is the problem.

Regarding rise time and ringing frequency; This is a area where I've heard lots of stuff - but not quite managed to separate the BS from the truth. A 14MHz ringing frequency would imply that the pulse that set it off was extremely slim; one period is ~70nSec. The rise time of the fets isn't slim enough to create this. The only culprit I can find is the body diode of the other fet - being shut down. Minority carriers will shut down in a fast and violent way - mosfets are irradiated and added precious metals to give them soft recovery properties - why would they if they didn't need to?

[liveforphysics]

Looks like a 9 volt supply would be OK. I think it was bigmoose who pointed out to me you want to be just about the miller plateau.

You MUST switch above the miller plateau by a healthy amount.

[Arlo1]

Looks like a 9 volt supply would be OK. I think it was bigmoose who pointed out to me you want to be just about the miller plateau.

You MUST switch above the miller plateau by a healthy amount.

Sorry post was suposed to say "above" no about. I will edit now. What is a healthy amount? 10% 50% ?????? Bigmoose pointed out on the robotics controller he diagnosed if they have to hi voltage and or to low gate resistor it will cause ringing!

[nieles]

got the snubber soldered in to place.
this is with a 2.2nf capacitor and a 8.3R resistor
battery voltage is ~40v

with snubber (1).jpg (37.33 KiB) Viewed 315 times

there is still 14v overshoot, if i want to lower that i need to increase the resistance right?

[Lebowski]

nope, remove the old snubber, double the cap to 4.4 nF, determine the new ringing frequency with the 4.4 nF and calculate the new snubber resistor.

The bigger the cap the less overshoot but the more power dissipation in the resistor.

Did you use only one snubber on either low or high side FET or did you snub both ? Snubbing both is the way to go.

Can you show a before (no snubber C or R) and after picture so we can see the influence of the snubber ?

[liveforphysics]

Just my $0.02, but I think you guys are doing the snubber concept incorrectly.

If I wanted to make that spike vanish, I would just increase the gate drive resistor value a bit, and add a fast zenner between source and gate set to a volt above my gate drive power supply voltage, and add a tiny ferrite bead around the leg of the gate.

Your initial rise slope wont be quite as steep, but your total time in the trans-conduction region will be reduced greatly (no more bouncy time), fet heat will be reduced greatly, and the durability and immunity of the circuit will be increased.

[Lebowski]

The picture shown by Nieles to me looks like a single FET has been snubbed, not both. With both it'll look even better.

Gate resistors, what I did was I snubbed the drain/source and then had a look at the gate-source signals. These looked
like textbook square waves with no overshoot, so I left it at that and did not add gate resistors. I do have one 10 Ohm
gate resistor in the DCDC converter because there I did see an overshoot on the gate/source (the gate resistor
reduces the overshoot). Except for reducing the gate/source overshoot (if at all) the only other reason I can see
for gate resistors is to reduce the power dissipation in the gate driver IC. The power dissipation in the gate drive
circuit is

P_diss_gate_drive = f_pwm * Q_gate_charge * V_gate_supply

The dissipation will not change with a gate resistor, but it can take some of the dissipation away from the gate driver IC.

In the controller I'm running on my bike at the moment (50 km and stil working yay !), the switching dissipation in the
FETs (no power delivery) is so low that a temperature rise in plain 4115's with no heatsink is almost undetectable. So
as far as this goes I see no reason to introduce a gate resistor to reduce switching losses. My FET's switch on in around
0.1 to 0.2 u-sec, I can reliably make sub u-sec pulses....

[nieles]

The picture shown by Nieles to me looks like a single FET has been snubbed, not both. With both it'll look even better.

i added a snubber to both the high and low fet.

i also have a 10ohm gate resistor, and a zener diode across G-S (although no idea if it is fast)

[liveforphysics]

Your switching loss won't show up until touching the plateau is actually causing current to flow.

[Lebowski]

Your switching loss won't show up until touching the plateau is actually causing current to flow.

but by that time the dissipative losses in the Rds_on should be much higher than the switching losses, no ?

[liveforphysics]

Your switching loss won't show up until touching the plateau is actually causing current to flow.

but by that time the dissipative losses in the Rds_on should be much higher than the switching losses, no ?

I would hope so, or you're not running it very hard. But this and only this is when the switching loss gets added. Only a tiny tiny percentage of switching loss is actually the act of charging and discharging the gate grid unloaded, it's when you trigger current and it pulls the source up and sends it back into the trans conductance region.

[Lebowski]

Your switching loss won't show up until touching the plateau is actually causing current to flow.

but by that time the dissipative losses in the Rds_on should be much higher than the switching losses, no ?

I would hope so, or you're not running it very hard. But this and only this is when the switching loss gets added. Only a tiny tiny percentage of switching loss is actually the act of charging and discharging the gate grid unloaded, it's when you trigger current and it pulls the source up and sends it back into the trans conductance region.

The dissipation in the FET is massive while in miller plateau so you should go through the plateau as quick as possible... I have a 2 Gs/sec scope with something
like 500 MHz BW and had to zoom in almost to the minimum timescale to see the plateau (which fits, 30 nC of a 4115 can be delivered in 15 nsec with a 2A driver)...

What do you call transconductance region ? isn't the transconductance the gm, like in delta_Id = gm * delta_Vgs ? AFAIK you have the triode region (when the FET
acts as a resistor) and the saturation region (when the FET acts as a controlled current source having a certain transconductance).

[bigmoose]

... it's when you trigger current and it pulls the source up and sends it back into the trans conductance region.

Bingo! I think you would benefit from gate resistors (3 to 4 to 10 ohms) and slowing down your edges, but that is just my opinion.