Endless Sphere

Of course I won't be able to out China China. You can totally out China, China. Just take someones money, send them a defective product, or the wrong product, or even better an incorrect defective product! Then when they ask for a refund, tell them sorry, but you'll provide them credit on their nex...

TI's Instaspin on their C2000 chips is really nice, but the code bas a fairly steep learning curve when you start using your own hardware. FOC Sensorless startup has worked on every motor I tried with a little tuning.

This is part of a series of tests I ran to quantify some maximum parameters of various MOSFETs. The one in this video is an IRFP4568. Turns out my setup was able to handle a maximum of about 120W of dissipation. Not going to happen once an insulator is in place, I only managed 66A when it was instal...

Any particular reason you want to run 17" rims vs 15 or 16"?

What about snubbers in this situation of ringing? I've had luck implementing snubbers in one of my low power controllers (mainly compensating for bad layout). Can snubbers scale up to high power stuff? There are high power setups using snubbers but it's best to design to avoid snubbers if you can (...

yes, additional capacitors on the DC bus rarely help. The PCB must originally be designed to accommodate all caps with low inductance. My observation was that the new low frequency (660kHz) is the oscillation between the big DC bus cap and the new 1uF, and the high freq (10MHz) is between the 1uF a...

From where do you see it is EMI sensitive, by the gate ringing? By your 475 and 575ns which transitions do you mean exactly, can you show on a waveform? From what you said, I thought you had an EMI compliance issue. The 475ns refers to the time it takes the D-S to switch from 10% to 90% of it's ran...

We have several designs going on in this forum so I'll share some troubleshooting tips which hopefully aid in the design/construction. There are many issues which crop up when paralleling devices, most of them tie back to layout issues and parasitic inductance. For more details on this topic I sugge...

That's some good info Peters. I too have seen that same oscillation on the miller plateau in some of my previous testing. The way I handled it was to add a larger Cgs cap as you mentioned, and it worked really well in my own application, but my application was not noise sensitive. It appears your ap...

I reckon there are several options: 1. gate driver with desat. This is the most robust protection. The ACPL-33x series is also a choice, functionally similar to ISO5452. I use ACPL-332 nowadays. The difficulty with both of them is that they require 15V power supply, but some FETs operate better at ...

Part you listed is obsolete. :confused: Here is the status of the part from ST micro, says it's still an active part https://www.st.com/en/power-management/td350e.html The reason I'm recommending this gate driver to you is not because it's a top of the line chip, it's because I've fully tested ever...

Search my username and td350, you'll have hours of reading.

galp wrote: ↑

Jul 26 2019 9:19am

IT's this one: http://www.ti.com/lit/ds/symlink/ucc21520.pdf

I would not use that gate driver, it's not suitable for this application as it provides no fault mitigation.

the gate drive signal is crossing through the power pass section which is a pretty big no no For clarification, are you referring to the power pass as the DC bus bars or the switch nodes going to the motor phases? The gate drive traces are passing through both of the these regions. If you are refer...

Personally I think it would be better to route the PWM signal around the power pass section to a separate gate driver on the other side, but I prefer reliability and robustness over ease of design. The gate driver layout is the most critical part of the entire design. If you manage to induce enough ...

It looks like the gate drivers on the bottom of the board and all on one half (high or low side). While this makes for easier construction, it also means the gate drive signal is crossing through the power pass section which is a pretty big no no when attempting high current. While I don't recommend...

Stick to 45A rms per device for to-247 and 35A to-220 devices for continuous operation and it "should" be ok based on my own testing. The leg temps tend to be about 10C hotter than when the case temp is 80C (which you don't want to exceed). Keep in mind that when I'm talking about continuous, i real...

My vesc used discrete drivers and amplifier.It's cheap and stable. That's really neat and but has jack all to do with the original question, why is the drv8302 "not good"? Personally I use a TD350E in several designs up to around 25kW, it's old, low cost and very robust (Miller clamp, negative gate...

I noticed that current drawn affected that magnitude of the spikes more than anything else. This makes sense being that the spike is a reaction to parasitic inductance which in turns increases in severity when there is more current involved. That is expected, but take a look at what happens when yo...

TEK0000.JPG Vsupply = 50.4V, I Motor = 46A continuous So I did a test at 50.4V with the motor under load. I picked up spikes of 61.6V under these conditions. Note that I could not use low-induction/low-noise measurement techniques as I did before for this test. I estimate at least 3V are attributed...

I'm using 10ohm resistors right now for the gates but maybe i'll try higher. I figured I would try and keep the rise/fall time combined under 1% of the switching period. This was some guidance given to me earlier in this thread. Not sure why 1% was suggested for this application, but typically you ...

You could reduce your ringing and possibly the need for snubbers by slowing down your switch off time. Looks like you are switching <100ns and you really don't need to. A good practice is to start around 800ns and start reducing the gate resistor from there. You should only switch as fast as you nee...

The conduction losses are the primary source of heat and only depend on current. Switching losses will go up with voltage. Overall, you won't see much change with higher voltage unless your switching times are too slow. I^2*R loses are dominant at high duty cycle, but at low DC Vds (diode) loses do...

10cm is not an issue for gate drive as long as it is over the proper ground plane (not possible on current design). Another possible compromise is to use twisted pair for your gate drive and eliminate the traces all together. The twisted pair will be much less likely to experience ringing. It also h...

One thing to keep in mind if you do not try to cancel these fields is you will become an intentional radiator. It doesn't look like it would take much to include a overlapping bus design while keeping that same style layout. Caps would most likely need to go on a carrier board with mechanical connec...