johnrobholmes
10 MW
I've been studying hardware and shall use this thread to hash out some ideas. I would appreciate any guidance on a concept circuit that generates a clock signal from two inputs. This would be nice and easy to do in software, which is why it is bugging me that I can't conceptualize the hardware equivalent :lol:
Two inputs will be used, a clock signal and a comparator out. When both clock and comparator are high, the output signal will be high. Once high, it will latch until the comparator signal goes low. AND condition to latch high, single input falling edge triggers reset to low.
Today's thoughts- may be accomplished with a master-slave D Flip Flop... inputs driving an AND driving the data input and the comparator driving the clock. Time to simulate! Wait, nope, don't think this will output the clock correctly...
Two inputs will be used, a clock signal and a comparator out. When both clock and comparator are high, the output signal will be high. Once high, it will latch until the comparator signal goes low. AND condition to latch high, single input falling edge triggers reset to low.
Today's thoughts- may be accomplished with a master-slave D Flip Flop... inputs driving an AND driving the data input and the comparator driving the clock. Time to simulate! Wait, nope, don't think this will output the clock correctly...