Gate driver design with TD350E

bdj

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While followed a thread "low inductance output stage construction", I decided to make similar set up and test. Along the way lot of things get improved and then come a question of good gate driver design. Decided to go with Zombiess design. Here is preliminary schematic with little modification. Design differs from original design in this post https://endless-sphere.com/forums/viewtopic.php?f=30&t=58341 in couple of things. I didn't used current boost stage with output transistors and added bipolar power supply.
350_gate_driver.png
Some application notes which used with a lot of info.
https://www.stmicroelectronics.com.cn/resource/en/application_note/cd00040938-using-the-demoboard-for-the-td350-advanced-igbt-driver-stmicroelectronics.pdf
https://www.thierry-lequeu.fr/data/AN1944.pdf
In original design driver was used with IRFP4568.
Concerning diode DZ1 I used same value of 7.5V. How this value was choosed? I understand that this value is involved in 2-level turn-off feature and Vgs voltage first falls to this value and after some configurable time falls to zero or negative votage (depends which power supply is used for driver). What are pros and cons using zener with higher value for example 10 V?
 
If you are going to be switching MOSFETs and <200V, I don't see an advantage to the 2 level turn off function. My suggestion is to set it up, but not populate it. In my latest design I left it out, however that was a mistake since I plan on using IGBTs at some point, so my next revision will have it, I've since added it back to the schematic as pictured here. The 2 level turn off voltage was chosen to be slightly above the maximum Vgs(th). After experimenting with it, I don't see the need for when driving most MOSFET based designs. A downside to the 2 level turn off is the delay is a fixed period on every PWM regardless of if there is a fault, this time needs to be accounted for in propagation delay and will reduce the maximum switching frequency you can run. Without it, you can set the dead time to 800ns and be safe under pretty much all conditions. I think when I calculated the 800ns dead time as safe I was still using it, so I might be able to reduce my dead time some more. My memory on this part is a bit fuzzy, I'd need to go look at the math again.

To make the schematic a bit easier to read, I'd suggest cleaning it up a bit. It's good practice to not join more than 3 connections at a single point. An improved method is offsetting the 4th connection which you can see in this copy of the schematic I'm using on my current 12 FET design. If you have parts which you don't plan to populate because they are for optional configurations, mark them as DNP for Do Not Populate.
Gate-Drive.PNG

I'm still using the 5V regulator, but it would be lower cost if I moved to a zener based regulator, however I was hesitant to make a change to a design which I knew worked for my current project. I'll be moving on to a more advanced gate driver in the near future, but I know the TD350E pretty well and have based many designs on it up to about 25kW peaks. When choosing a DC-DC converter, make sure you get the unregulated type. Regulated types can sometimes run into oscillation issues, never seen it myself but I've been warned about it.

What current / voltage level are you shooting for? You most likely don't need the -9V bias on turn off due to the miller clamp being quite effective, the exception might be if your power device has a low turn on threshold, some devices turn on <2V so negative bias could be beneficial. A quick warning on negative bias is that it really shortens your turn off time, so it requires a higher value resistor for turn off.

Speaking of gate resistors, just spec them out to be 2512 sized. It's difficult to get rid of any heat which builds up in gate resistors. I have all the formulas for calculating this, but I just plop a 2512 down and call it done because I haven't been space constrained. Most likely not a problem, but it's good practice to oversize the gate resistors. It's also easier to swap them out when tuning on the bench. You can also get by with just a single 10uF cap on the supply rails. In my latest design I'm only using a 2.2uF and have had no issues switching 2 paralleled devices at 50kHz.

Feel free to ask any questions. The real fun starts when you get to PCB layout.
 
Okey I took suggestions and here is updated schematic.
317655B5-973F-4997-B730-11AFC4439CD6.jpeg
Concerning 2 level turn on I want to evaluate it but for now I won’t use it. Concerning DC-DC converter for this testing I plan to use transformer power supply with linear adjustable regulators positive and negative lm317 and lm337. I have couple of these power supplies already assembled. So -9V is just for testing and plan to test with other negative values too regarding datasheet of gate driver. When you talked about dc-dc you meant on switching reg? Could oscillation issues be also with linear reg in gate driver scenario? I read that linear reg can oscillate when not provided good bypassing.
Plan is to use driver for voltages up to 100V and currents up to 30-40A.
Here is some preliminar layout.
950E4FA8-4ABE-477A-92A8-4411D6084141.jpeg
When high fet is on and lower fet is off on its drain would be voltage almost equal to power supply voltage right? So clearance should be taken into the account concerning path drain-zener-blocking diode? Are there any other constraints concering pcb layout if plan to work with higher voltages up to 400V?
 
The regulator comment was something I've been told. You probably won't have any issues, but based on who told me I'm taking his word for it that oscillations can happen.

It's generally bad practice to run a trace into your isolation zone. It would be better to route that trace around the front, even it means using vias to stitch it through. This is less important at lower voltages, but I'd suggest starting out following good practices.

Anytime you are dealing with higher voltages you need to follow creepage and clearance recommendations.
http://www.pcbtechguide.com/2009/02/creepage-vs-clearance.html
 
Ok, I made correction concerning isolation zone, clearance and creepage. Here is new layout.
E8EC5054-FF7D-43F9-BF1E-EE40DEA0D14B.jpeg
I will send it to manufacturer and hopefully in a two weeks get back with results if board is working and some test data.
 
Boards are finished and some test were run.
F9E4796F-9DBC-4A5A-8424-7A8860367C32.jpeg
EC30813A-4D0E-46DA-AF0F-2A2AD2065436.jpeg
Power supply 60V and current 40A.
Here are Vds of low and high fet.
73907543-56C5-478F-970E-41F47CE4E802.jpeg
259D56BB-1E92-43B7-B1FC-3D23122B45A0.jpeg
High fet Vgs
C3C205FC-1B3B-40E0-9DC9-6A0DB95FAD5F.jpeg
01367202-06FA-4986-8226-BC441340DA8F.jpeg
Low fet Vgs
8ECE85BF-7191-4238-99B1-118876A62AC5.jpeg
359096B0-306A-4919-909D-ACBF28A635C7.jpeg
5FCD3D2F-5918-47C1-8F4A-E0D04EF372C9.jpeg
Low fet driver isolated linear power supply 15V and -3V
High fet driver isloated linear power supply 12V and 0V
GS caps high side 10nF, low side 20nF
Turn on/off resistors same for both drivers 12R.
Desat and two-way switch off disabled.
Twisted wires for gate drivers about 10cm long.
Used regular probes no shortened gnd clip on probes currently.
Dead time set to 1.2uS.
Suspect that some noise was picked up especially in pictures of dips and bumps of low fet Vgs.
DC bus cap 2200uF electrolit and close to fets 1uF block.
Soon I will test it with dc bus polypropylene cap 4.7uF and shortned probe GND clip.
As soon as I get components plan to put same levels of power supply 15V and -3V to both drivers.
 
Still a surprisingly fast G-S switch speed, well under 100ns. If you could slow that down some more it would clean up some of your ringing. Now you need to experiment.

I'd suggest making the gate leads as short as possible and compare. You want your experiments to be repeatable, so use a fixed coil and send individual pulses. In a double pulse test you turn on for a given period of time to let the current rise to your desired test amount, then turn off and wait until everything settles, I usually use around 20us, then turn on again into the circulating current so you can observe how thing look switching into current. If this is all controlled, then any differences observed should only be caused by changes you are making, allowing you to see what makes it better or worse.

You can build a double pulse tester with an arduino and a few delay timers turning a pin on and off.

To figure out your target current, you can temporarily place a shunt in line or use a hall effect contactless current sensor hooked to your scope. My load coil is usually a small air coil made from a spool of wire. Measures at 25uH, i suggest yoy stay > 25uH for now.

Also, keep the power leads to your power stage as short as possible, they will add to any ringing. Items which are often unimportant in most circuits can become critically important in power electronics.
 
I tried with shorter gate leads. Everything is same 60V and 40A.
734C4B99-3479-477E-A6A7-0E74AD84D391.jpeg
Lot of improvement. Here is low fet Vgs with dips and bumps. Firs disturbance reduced by 2V both positive peak and negative peak.
12FC0340-B7AC-4FF2-9D80-2A0C47D46463.jpeg
76CDD83C-44D5-445A-82CD-88429ACEC2C9.jpeg
120C32BB-9BE3-4B5A-A630-A5F715ACC73D.jpeg
Noticed that high fet fall time significantly reduces from 1.2uS to 0.4uS when fet switching high current.
Here is high fet Vgs falling edge. Supply 60V and 9A.
5B356403-C1B4-415A-AF73-F2064459AA8B.jpeg
Here is same graph but with 40A.
810DB344-B34A-4F33-BBB9-797E83A0E8F6.jpeg
Is this behavior expected or it is issue? How this could be explained? Rising edge looks same in both conditions. Maybe UVLO of TD350 is kicking as high fet driver power supply is 12V. I will check fault output and try with 15V supply.
Concerning pulse testing plan is as you suggested to go with coil but with high power serial resistor (form 0.1 to 1R depending of L, pulse width and wanted current). If use small value shunt, noise will eat signal, if go with hall I wouldn’t see all changes because currently have couple of them with small bandwidth about 50KHz and read it here in some posts that max bandwidth of hall is about 200KHz.
 
bdj said:
Is this behavior expected or it is issue? How this could be explained? Rising edge looks same in both conditions. Maybe UVLO of TD350 is kicking as high fet driver power supply is 12V. I will check fault output and try with 15V supply.
Concerning pulse testing plan is as you suggested to go with coil but with high power serial resistor (form 0.1 to 1R depending of L, pulse width and wanted current). If use small value shunt, noise will eat signal, if go with hall I wouldn’t see all changes because currently have couple of them with small bandwidth about 50KHz and read it here in some posts that max bandwidth of hall is about 200KHz.

As you go up in current, you excite more resonance in your circuit, this means more noise. You are also making your measurements with standard probes, so there is always going to be additional noise vs using a differential probe. If you hit UVLO, you get nothing, so that should not be an issue. Gate drives do not require much power, their peak current is demanded from the main supply cap on the VH pin. This cap placement should be within 2mm of the IC which it looks like it is in your layout, but loop area could be improved. Layout priority should be given to this capacitor and it should have as small of a loop area as possible.

When measuring switching times, look at the time it takes to switch from Drain-Source, this is the signal being referenced in switching time.

Pretty amazing the difference a few centimeters of wire makes. It's all about loop area and managing inductance wherever you have a high dI/dt signal. I would suggest moving to 2512 or some other SMD based resistors to help reduce inductance, you want them as close to a ground plane as possible.

Moving to isolated DC-DC converters on your gate drive will probably reduce noise issues even more. The design goal is to keep noise out and to not generate additional noise. Switching devices can cause ground bounce.
 
You were right, checked FAULT signal it looks good so no UVLO.
zombiess said:
This cap placement should be within 2mm of the IC which it looks like it is in your layout, but loop area could be improved. Layout priority should be given to this capacitor and it should have as small of a loop area as possible.
You mean that loop area could be smaller by shorter path from caps to GND pin of driver? As we are speaking of layout could you explain little bit source connection from your design?
gate_driver.png
Shouldn't be gate driver connection to source done only in one point? What is achieved here with multiple connection from driver to source? High current from fet source will go through path of minimal resistance (on the middle of board left HS_HS_HS) and then high current influence would be smaller on other source connection (bottom left HS and HG)?

zombiess said:
When measuring switching times, look at the time it takes to switch from Drain-Source, this is the signal being referenced in switching time.
This is important concerning measuring, calculation of power losses and heat while fet switches like in picture below?
power_losses.png

Concerning 2512 resistors I ordered them so they will come in 2-3 weeks. DC-DC wires can be reduced but already everything is close enough so plan to do this when make pcbs for power stage.

I make a coil and measure inductance and resistance. This is cheap meter from aliexpress but it can give some guesses. I could go with calculations of L based on length, wire diameter, number of turns but didn't checked yet as I get some "good" shoots of current from scope.
R = 0.1ohm L = 70uH
image0.jpeg
Currently haven't available power resistor but small value shut. 100A ~ 75mV
image2.jpeg
Here are some shoots of current through air coil.
image5.jpeg
image6.jpeg
image7.jpeg
So from pictures can be seen that current is 52mV * 100A/75mV ~ 70A just before falling edge and 32mV * 100A/75mV ~ 42A just before rising edge. Seems that coil has enough inductance and resistance as current doesn't fall to zero (except when switching ).There is a lot of noise when fets are switching so I will try to find some higher resistance shunt for example 10mR. When do the pulse testing maybe I can go with some power resistor if it don't heat much and not change it's resistance under small pulse ~ 200uS -300uS.
Next thing which I tried was putting 4.7uF PP cap on dc bus instead old one electrolytic cap 2200uF. Maybe I misunderstood but get a sense in some posts that 1uF of PP cap is enough for 1 KW? Was this referred to battery powered applications where battery itself has small resistance and inductance in compare with my setup with transformer power supply with rectifier caps? 4.7uF PP cap was measured with cheap LRC meter and showed 4uF capacity. Here is picture of low fet Vds.
image9.jpeg
Time base is 5uS so rising edge overshoot can not be seen but it is about the same as with old cap. Could drop of voltage and big oscillation be explained by that power is drawn from rectifier caps and inductance and resistance of wires and rectifier caps cause this ?
Next I would read some docs about double pulse testing and program mcu.
 
bdj said:
You mean that loop area could be smaller by shorter path from caps to GND pin of driver? As we are speaking of layout could you explain little bit source connection from your design?

General rule of thumb is to keep all loop areas as small as possible. This becomes much more important as you go up in power.

Shouldn't be gate driver connection to source done only in one point? What is achieved here with multiple connection from driver to source? High current from fet source will go through path of minimal resistance (on the middle of board left HS_HS_HS) and then high current influence would be smaller on other source connection (bottom left HS and HG)?

I've done both, never really noticed a difference, but the connections have always been done Kelvin style. No part of the gate drive trace enters the power pass.

zombiess said:
When measuring switching times, look at the time it takes to switch from Drain-Source, this is the signal being referenced in switching time.
This is important concerning measuring, calculation of power losses and heat while fet switches like in picture below?
power_losses.png

Power loss would be calculated by integrating the current and voltage wave forms and multiplying them. This is not something I typically have worried about myself as conduction losses usually dominate at high current and low switching freq. Start switching at +50kHz and that might change, it's on a design by design basis. Slower switching = more losses, but less noise generation. General rule of thumb is to only switch as fast as needed, and only at as high of a frequency as needed. Lower inductance motors or not enough DC link cap ripple capacity can necessitate a higher freq. My finger will often tell me if I'm pushing it too far, or if something comes unsoldered, or turns to smoke :)


Next thing which I tried was putting 4.7uF PP cap on dc bus instead old one electrolytic cap 2200uF. Maybe I misunderstood but get a sense in some posts that 1uF of PP cap is enough for 1 KW?

Are you talking about using a cap as a snubber? I don't usually add additional caps to the power rail beyond the DC link as they can cause LF oscillations on the DC bus; the DC link is calculated based off inductance of driven load, demanded ripple current and switching freq. Highhopes has posted the math on this site on how to calculate the minimum required. Beyond that I've been experimenting with RCD based snubbers acting as a voltage clamp and can recover 50% of the energy. Need to use a Spice program to figure out the right values after you calculate the parasitic LC of the DC link which can be done by monitoring the ringing frequency, adding an additional cap D-S on a device and seeing the change in ring frequency. Check out Nexperia AN11160 for instructions on how to do it.
https://assets.nexperia.com/documents/application-note/AN11160.pdf

For double pulse testing this explains the prodcedure
https://www.powerelectronics.com/technologies/power-management/article/21864518/evaluate-power-device-efficiency-with-doublepulse-testing-using-an-afg

The hard part with pulse testing is getting good current readings, but just having voltage reading is better than nothing. I purchased micro Rogowski coils for my research, but they are pricey going for around $1k each, and I needed 2 :(, but I love them :mrgreen:
 
zombiess said:
I've done both, never really noticed a difference, but the connections have always been done Kelvin style. No part of the gate drive trace enters the power pass.
Good to know :thumb:
zombiess said:
Are you talking about using a cap as a snubber?
I was talking about dc link cap. My mistake, recommendation was 10uF of PP cap per 1kW not 1uF. Yes I saw the math from Highhopes and also from this document https://www.ecicaps.com/wp-content/uploads/IEMDC_2009_11310_Final_Rev_4.pdf and peter's approach. Do you have some shoots of current from battery, current thorough DC link cap and current from DC link cap to high fet? Did some measurements of current through DC link cap with shunt of 10mR just to have insight what is going on and to verify with simulation.
First is low fet gate Vgs other pictures are DC cap current.
image0.jpeg
image1.jpeg
image3.jpeg
I didn't come yet to this point but plan is to investigate this further when come to build power stage and layout.
zombiess said:
For double pulse testing this explains the prodcedure
https://www.powerelectronics.com/techno ... ing-an-afg
Nice explained. I have come up with another one with some proposals https://eepower.com/technical-articles/double-pulse-testing/#.
From text "To measure the DUT voltages as shown in Figure 2, it is possible to use single-ended probes. Figures 4 and 5 show some techniques to reduce loop inductance and coupling in the measurement path and how some turns around a ferrite core can add common mode impedance to the measurement signal."

What do you think about this solution? Did you had a chance to try? Details about dimension of ring are not shown but could be find out approximately.
probe.png

I am currently still preparing for double pulse test. In some app notes find out that even shunts could be only acceptable for lower currents as add inductance so no power resistors in consideration for current measurement.
zombiess said:
I purchased micro Rogowski coils for my research, but they are pricey going for around $1k each, and I needed 2 , but I love them
I believe :) currently my budget for this learning isn't so high so I plan to try cheap coils from aliexpress to see what I can get.
 
Here is setup for test. I left 2 huge shunts for current mesurement of dc link cap between - of cap and ground and between source of lower fet and ground. Source and gate of higher fet connected short.
40A642ED-F4D4-4941-9D8E-BE8CC193F075.jpeg
Vgs of lower fet.
8A2ED717-163C-447D-B58E-76A1DECED8C3.jpeg
Vgs of lower fet second edge.
9128F0C3-F3C1-4B8F-9187-9E885B00457E.jpeg
Vds of lower fet.
1342ACD7-6783-4C69-9D9E-D3936E3B3FC1.jpeg
3B73A67D-5AE3-47EF-889E-30777941C657.jpeg
Current of lower fet.
C93D1D63-C050-41CD-9BA1-0B2A48054895.jpeg
Current of coil.
41E2A19E-ADB9-48E9-812E-70F380685D54.jpeg
Concerning current measurements 10mV are 1A. All in all lot of noise, inductance and oscillations. Concerning Vgs measurements I hook a ground clip on shunt as I could not reach source directly so this also influenced measurements. Next I will get rid of all shunts except one which measure coils current and do test again.
 
You can't really use those measurements with the shunts for a whole lot as they act like added inductance. The measurements really need to be made with a contactless probe. Maybe a small carbon (needs to be pulse withstanding) resistor could possibly provide better insight, however just seeing the Vds and Vgs wave forms can provide quite a bit of info. They do tell you the current ramp rate for that setup though, so you can now calculate how long to pulse the setup for to reach a desired current for testing.

That turn on noise looks pretty significant, but it's difficult to determine how much of it is real without a differential probe. I've found minimizing this turn noise can be tricky.

Have you calculated your layout inductance yet? If not, measuring your ring frequency at turn off after overshoot, then add 20-100nF across Drain and Source of the MOSFET you are pulsing and measure the ringing frequency again. It should be significantly lower. Go through the math in the Nexperia document I linked to, or just post the ringing frequencies here and I can plug them into my spreadsheet. Then remove the shunts and redo the same measurements, this way we'll have some idea how much inductance your power pass section has. I'm super curious to see how much the shunts you installed added.

I have 2 PCB based bus layouts of similar geometry, but different sizes and both have about 20nH of parasitic inductance. One is my controller I posted about, the other is a high current (30A) boost converter. Two previous copper based laminated layouts I've done had around 60nH.
 
Yes I will try with carbon resistor. I figure it out also that I would need diff probe so I order cheapest solution micsig dp10013. When it comes I will do tests again. I shortened gnd clip and better place probe concerning Vgs measurements and get a better results. Still didn't succeed to place right where pins exit the package (still have at each place (G and S) 5-6mm respect to package ). When do pcb will have more opportunities. Measured dimension of two copper sheets are 35mm x 20mm and distance between them is about 0.03mm. Placing into page you posted http://www.pulsedpower.eu/toolbox/toolbox_inductances.html gived some low results 0.06597344572538565 nH. Differences is that I have between copper sheets two layers of capton tape.
Current setup measurements with better placed Vgs probe.
image0.jpeg
Vds voltage
image1.jpeg
image2.jpeg
Same measurements when added 100nF between low fet D and S(just bare cap without any dumping resistor)
Vgs voltage
image7.jpeg
Vds voltage
image6.jpeg
image4.jpeg
Then removed a DS cap and all current shunts.
Vgs voltage
image16.jpeg
Vds voltage
image12.jpeg
image11.jpeg
Then added 100nF on DS
Vgs voltage
image15.jpeg
Vds voltage
image13.jpeg
image14.jpeg
Adding bare cap across DS worsened things and some high freq oscillations appear. I am thinking that i am pulling max from this setup as there are a lot of wires connecting smd caps, gate driver, probes gnd..I am planning to test couple more things in this setup as slowing down switch speed and test with diff probe but when get all parts. In meantime I plan to do layout for power stage based on your design.
 
bdj said:
Measured dimension of two copper sheets are 35mm x 20mm and distance between them is about 0.03mm. Placing into page you posted http://www.pulsedpower.eu/toolbox/toolbox_inductances.html gived some low results 0.06597344572538565 nH. Differences is that I have between copper sheets two layers of capton tape.

What are the ringing frequencies with and without the 100nF (not just screen shots)?
 
bdj said:
Measured dimension of two copper sheets are 35mm x 20mm and distance between them is about 0.03mm. Placing into page you posted http://www.pulsedpower.eu/toolbox/toolbox_inductances.html gived some low results 0.06597344572538565 nH. Differences is that I have between copper sheets two layers of capton tape.

What are the ringing frequencies with and without the 100nF (not just screen shots)?

I like to record my lab work on video and call out my observations so i can review them later when I forgot what I found.
 
Without cap ringing frequency is 500KHz. With 100nF cap ringing is also 500Khz + fast damped ringing of 5MHz on rising edge.
 
Could you remove and G-S additional capacitance you have and do the D-S scope shots again? We want excite ringing so we can learn more about the parasitic components of your layout, well at least I do and it's good information for anyone following along.

Without the G-S cap, you should get observable ring after turn off, right now it looks like it might be critically dampened. With the addition of the 100nF D-S across the pulsed MOSFET the ringing frequency after turn off should drop significantly, reduce the value if 100nF looks like too much.

So adding the D-S cap caused an additional high frequency ring, I don't think I've seen that before, but I suspect it would be from the 100nF + Coss and the leg inductance forming a LC tank as it looks low energy. The 100nF D-S is only a temporary thing done to alter the ringing frequency so we can find out more info. This information is useful in snubber design as well as you can setup Spice simulations which closely mimic your actual layout and play around with values and observe power dissipation requirements / tweak values.
 
Okey. I removed GS cap and go just with 100nF on DS.
Here are results.
Vds voltage
0DB9EB6A-061E-4A9D-9CB3-F493BBA310DA.jpeg
Vgs voltage
D449EDFE-4497-4A02-AE5E-8569F001D501.jpeg

Then I removed 100nF and put 33nF on DS.
Vds voltage
906BD16D-B687-4A58-B8FD-D1D20B4B77F2.jpeg
Vgs voltage
A94900EE-B095-4DA3-8824-D39E4973823A.jpeg

Vds(with added 100nF on DS) reaches overshoot of 28V and ringing frequency was 5MHz.
Vds(with added 33nF on DS) reaches overshoot of 44V and ringing frequency was 7-8MHz.
Concerning power stage, should I open new thread? Here we can continue testing.
 
Remove all capacitance D-S and G-S, what frequency does it ring at?

Did you read the app note i referenced? The D-S capacitance is only added temporarily to alter the ringing frequency. It purposely makes the ringing worse. After you know the frequencies the cap is removed, a small amount (just enough) of G-S may be added to dampen some turn off overshoot if needed.
 
Now I have read it detaily. Followed setup and experiment explained in first couple of pages.
Removed all caps and measured ringing frequency of Vds on falling edge of low fet like proposed in document.
Here are shots of Vds(low fet).
C6376FCB-09ED-4B41-9330-F9F556FC6F13.jpeg
3908DEE5-5BB1-4EBD-A517-1F33C3CEA93C.jpeg
Ringing is 40.9MHz

Then added 33nF to DS of high fet and do measurements.
97248732-C2FB-48E3-B0DC-72703644D7DC.jpeg

Now ringing is 6.09MHz.
Calculated Clk is 750pF.
Calculated Llk is 20.18nH.

Checked Llk for both cases without cap and with added cap and it is same.

Here is shoot of rising edge of Vds with no added cap by shape looks similiar to your results from some post.
990B75FA-E890-44F3-BA38-7696C96F3FED.jpeg

Order of steps :
1. Low fet turned on
2. Low fet turned off
3.Low fet turn on
In point 3 all shoots were taken on falling edge of Vds. High fet GS was shorted all the time. Turn on and off times and sequence is same used in double pulse test.
 
Excellent! I suspected it was going to come in around 20-40nH, nice to see it's on the low end!

Now you have a really good picture of what you are working with, and can calculate snubber values if you decide it needs one.

This is a game of eliminating variables, and layout parasitics are a big unknown for most DIY builders.

You could re-install your G-S cap you found worked well and play around with the desat feature next. They way I typically test desat on a new gate drive is to set it to a much lower value than 1.5-2x the expected max current (like 0.5-1.0x), then I keep increasing the pulsed current until I see it trip. The reason I do it this way is to minimize the chance of popping something if I made a mistake somewhere. Once I see that it's working correctly at the lower voltage, I'll usually replace the load coil with 10-20 cm of wire which will induce a short and cause very high current. The desat should catch this and only let the pulse last for maybe 5-7us. Once I see this working, I'll then swap out the zener to a value which is around 1.5x the max current I expect to run and then test through pulsing again, then a short circuit again. Once I see it regularly passes these tests I tend to call desat good, then I move on to testing fault handling on the controller/hardware side. I personally have high confidence in the TD350E as I've worked with it quite a bit, but on a new driver I'll run additional tests to see how it performs on power disconnects where the only energy left is in the DC-Link caps, UVLO, verify Miller Clamp engagement, 2 level turn off, etc.

This whole process goes so much faster the 2nd and 3rd time. You want to have good confidence in your gate drive function as it is the most critical part in a controller.
 
Thanks for pushing me :) I see big benefit of last test. Yes next I will go with desat. First to read again as there is lot of info here about desat(and calculations) and then will follow your recommendations.
 
bdj said:
Thanks for pushing me :) I see big benefit of last test. Yes next I will go with desat. First to read again as there is lot of info here about desat(and calculations) and then will follow your recommendations.

I'm glad to see you think it is worth while. I know it's a bit confusing at first. A double pulse test really gives you a lot of insight into how the power stage and gate drive behave under consistent, repeatable conditions.

Just wait until you see Desat working, you'll never want to design without it again.
 
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