Okay, I need to find some extra inner peace to get that one. Will simulate.zombiess wrote:you'll need to have a diode across the inputs of InHS+ and InHS- and another on InLS+ and InLS-
Neither do I, its a bag of cats. I've seen rad hard fpgas running stress tests for months, tons of redundancy, cycle-by-cycle parity check of ram and wishbone buses, and the constant assumption that a stupid particle would flip a bit in your ram, or program counter if you have one. Its not pretty.the logic gates are there in HARDWARE external to uC because i do not trust software
About the logic... I think I'll remove it from this board and add it to the brain board, run high/low signals differentially from brain to gate. This way I can know and block PWM overlaps.flag notification. you'll probably need to consider somehow to latch that because it will come and go perhaps faster than uC can pick it up.
exactly. noise won't do this but it does still ends in same result by different path potentially and the logic gate (or other hardware method) protects against that. its all of these types of failure modes that need to be thought out and build in a solution for (its a long list, ha!). by the time you're done it is surprising though to see end up with 20% more cost to accommodate all of it which to me is probably a cost you can justify quantitatively even at high volume production. its basically statistical at that point.. what is your MTBF, warranty etc. and you can just do the math to find the break even point. what i have found is adding the extra safety is always in your favour financially and obviously for other reasons too so to me it always was a no-brainer. but then i was not in a race to the bottom for $ so i dunno, it depends on the market you are targeting and the risk you can take with that market. i can not design for cheap, that is an art in itself that i have no experience with.Neither do I, its a bag of cats. I've seen rad hard fpgas running stress tests for months, tons of redundancy, cycle-by-cycle parity check of ram and wishbone buses, and the constant assumption that a stupid particle would flip a bit in your ram, or program counter if you have one. Its not pretty.
technically you'd probably use a CPLD for this but... now we splitting hairs.1 fpga chip rather than logic gates everywhere.
Yup, he's right.technically you'd probably use a CPLD for this
i don't have enough thumbs for TI.Thumbs up to wurth and texas instruments
* = 6W rating only valid on 0 ohm valuesmarcos wrote: Vishay sells an equally magic 2512 6W* resistor.
I plan to weld the capacitor leads to the copper sheetszombiess wrote:How are you making the DC link capacitor connection to the copper bus and the power devices? I've always found this to be somewhat challenging. I have proper soldering tools that allow me to solder to thick copper bus, but this technique does not seem good for production. I'm interested to see what you have.
And its only doable if I get to think through all the steps and fixtures needed for a repeatable assembly. There is a fixture that hopefully holds the components and layers together in order to be soldered to the laminated bus bar. I'm not aiming at mid nor high volumes anyway.HighHopes wrote:your cap to bus connection does not look viable at mid to high volume and a pain but doable at low volume with great care. in marketing speak this means you have a design weakness that if someone else did better (read cheaper and/or more reliably) you might lose competitive edge.
+1marcos wrote:Oh, and something important I forgot to add: I licensed the project under CERN open hardware license (OSL).
DIY is always the best reading Great to see another thread on hardware design.Arlo1 wrote:Hey this is cool... A thread on ES that's exciting again
Sorry, I don't follow what you said about signals and resistors and sides.Arlo1 wrote:Hey this is cool... A thread on ES that's exciting again
Lots of good info.
I have one question are you sure you want to wrap the gate signals around like that....?
I mean you have the driver on the 1 side of the gates why not keep the signals and resistors on the same side as the driver at least this will help the 1 side of each phase leg.
With laminated boards/system it might be ok anyways but it looks like a trace running parallel to the phase/HV and higher power stuff which will want to absorb the noise and mess with your gate control.