Cheap FOCer (VESC 4.12 based design)

wil said:

Looking at your photo it looks like already had the via thing suggested above?

What is your approximate BOM cost for this iteration?

You can always just drill out the holes to fit thicker wires, it's not like the tiny extra amount of contact gained by the PCB depth being coated really adds much in the overall scheme of things.

Click to expand...

Right now the BOM cost is $30ish USD. That's the boards and components and utilizing the "free sample" technique I mentioned before. I haven't factored in cost of wires, connectors, and other hardware yet. Yes the via thing was already there in the design for thermal management reasons. I didn't have the soldering technique in mind mentioned by BotoXbz. Agreed that one can just drill the holes out for this version but I will be making another revision with all the minor tweaks and lessons learned from this one. I want 12awg wire to fit comfortably and maybe even 10 awg.

Hello

I am interested to have one populated board for testing. I will pay the BOM and shipping.
I have various e-bikes and electric car.

Please let me know if you are interested.

Cheers

pavlik1 said:

Hello

I am interested to have one populated board for testing. I will pay the BOM and shipping.
I have various e-bikes and electric car.

Please let me know if you are interested.

Cheers

Click to expand...

PM sent and was responded to.

Additional thoughts for this and future controllers:

I want these to able to fit in 1590B or other common aluminum enclosures. These are widely available for decent prices. The current design would only fit in a 1590B2 due to the height of the 1000uF capacitors. I could swap them out for the shorter 680uF caps and it would most likely fit in a standard 1590B. I could also alter the design slightly so that the caps can just lay down over the board, but that bothers me for some reason and idk why. There are also IP65 versions of these enclosures called the 1590WB. They simply have a gasket on the lid and o-rings on the screws. This will help keep dust and moisture out of the controller. Additionally, the enclosure might be able to retain mineral oil inside. I have been playing with the idea of utilizing mineral oil for improved heat dissipation of the whole controller board. As long as I use proper cable glands I think this is possible. Doing this could increase the current limits of this and future designs by a fair amount. Let me know what you think about this!

Gland or not the oil will wick down the wires and out of the enclosure like that.

Also I noticed you have thickened up the traces from the driver circuit to the FET gates, but only on G1, G4, G2. Any specific reason?

When you were designing did you consider having the high and low side FETs on opposite edges of the board? You could shift all logic down one end, + have smaller extra caps closer to the actual FETs themselves. I think you could also fit a 12 FET design into a maybe 30% longer board this way. In addition having the Caps closer to the FETs can eliminate ringing caused by the supply line inductance when they switch.

wil said:

Gland or not the oil will wick down the wires and out of the enclosure like that.

Also I noticed you have thickened up the traces from the driver circuit to the FET gates, but only on G1, G4, G2. Any specific reason?

When you were designing did you consider having the high and low side FETs on opposite edges of the board? You could shift all logic down one end, + have smaller extra caps closer to the actual FETs themselves. I think you could also fit a 12 FET design into a maybe 30% longer board this way. In addition having the Caps closer to the FETs can eliminate ringing caused by the supply line inductance when they switch.

Click to expand...

Bummer to hear about the oil wicking down the wires. Had my hopes up...but maybe I'll find a way still.

I was going through thickening the gate drive traces, then stopped for some reason, then entirely forgot to finish the rest before having boards made. In other words, I messed up on that. That will be fixed in a future revision of this design. Hopefully it still functions decent enough.

The general FET layout was based off of existing designs that I knew worked. I didn't want to try anything too crazy since I don't have any experience with designing these kind of electronics. I do intend on having caps closer to the FETs in the high voltage design like the VESC 6. Wouldn't spreading the low side FETs from the high side FETs out from each other across the board be non-ideal for current flow?

Found some good documentation on controlling ringing on MOSFET switch nodes. I have updated the PCB and schematic to have a 1206 100V ceramic cap by each set of 2 MOSFETs. These will be my snubbers to help reduce ringing during switching. I will measure any ringing during testing to make sure it's not excessive. My HV(high voltage) design will be more optimized to reduce loop inductance and minimize ringing at the root of the problem.


https://e2echina.ti.com/cfs-file/__...iques-for-NexFET-high-performance-mosfets.pdf

So what DRV chip did you decide to use? The DRV8353?

Let me know if you need more testers, I'm happy to. Or you can join the https://www.electric-skateboard.builders and post your project here. We are always looking for new stuff like this

melonfrog5 said:

So what DRV chip did you decide to use? The DRV8353?

Let me know if you need more testers, I'm happy to. Or you can join the https://www.electric-skateboard.builders and post your project here. We are always looking for new stuff like this

Click to expand...

The DRV8353 is what I'm using for the HV version as of right now. The HV version is still just a half done schematic/PCB in KiCAD right now so it's not set in stone. I've seen the eSk8 forum but I wasn't sure this belonged there. Is it eSk8 stuff only? If so, do you think my version of the VESC isn't too bulky for e-skate purposes? If you think me posting over there would be accepted then I'll do it. I'll PM you about testing.

shaman said:

Wouldn't spreading the low side FETs from the high side FETs out from each other across the board be non-ideal for current flow?

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Shouldn't really matter, you already have huge inductance from the motor and the long phase wires, an extra couple of mm of trace won't make a difference IMO. Your currents are limited by the thickness of the FETs legs here anyway (well and the FETs)

wil said:

shaman said:

Wouldn't spreading the low side FETs from the high side FETs out from each other across the board be non-ideal for current flow?

Click to expand...

Shouldn't really matter, you already have huge inductance from the motor and the long phase wires, an extra couple of mm of trace won't make a difference IMO. Your currents are limited by the thickness of the FETs legs here anyway (well and the FETs)

Click to expand...

Maybe you're right though I feel like having FETs on opposite sides of the board would make it hard to utilize the enclosure as a heatsink. The enclosure interior width would have to be just right so that one could thermally couple the FET tabs to the walls. Also it would seem like I would have to separate the high current supply and ground traces a fair bit to reach the opposing FETs. This would work against my goal of trying to minimize ground loops and parasitic inductance. However, I may be completely overthinking this or misunderstanding what you're suggesting entirely.

shaman said:

wil said:

shaman said:

Wouldn't spreading the low side FETs from the high side FETs out from each other across the board be non-ideal for current flow?

Click to expand...

Shouldn't really matter, you already have huge inductance from the motor and the long phase wires, an extra couple of mm of trace won't make a difference IMO. Your currents are limited by the thickness of the FETs legs here anyway (well and the FETs)

Click to expand...

Maybe you're right though I feel like having FETs on opposite sides of the board would make it hard to utilize the enclosure as a heatsink. The enclosure interior width would have to be just right so that one could thermally couple the FET tabs to the walls. Also it would seem like I would have to separate the high current supply and ground traces a fair bit to reach the opposing FETs. This would work against my goal of trying to minimize ground loops and parasitic inductance. However, I may be completely overthinking this or misunderstanding what you're suggesting entirely.

Click to expand...

Not at all, all of the things you mention are valid and should definitely be taken into consideration.

Heatsink wise as you are using a metal spacer I think the give you will get just from the FET legs will be enough to account for sizing.



Excuse it being hand drawn (and my handwriting, it's 2019, who writes by hand...) but this is essentially how I was picturing it for a 6 FET design. You will probably also want to run a GND up to the high side FETs for capacitors, VCC to low side, eg

If these are SMD caps you can have them literally touching the leg of the MOSFET on the bottom, then have a larger cap on either side to help hold these secondary rails at their respective voltages. I think the BESC does something similar with caps increasing in size as they get further from the FETs.

Benefits are essentially half the power carrying bus length for power and ground, and obviously the packaging being the major one.

wil said:

shaman said:

Wouldn't spreading the low side FETs from the high side FETs out from each other across the board be non-ideal for current flow?

Click to expand...

Shouldn't really matter, you already have huge inductance from the motor and the long phase wires, an extra couple of mm of trace won't make a difference IMO. Your currents are limited by the thickness of the FETs legs here anyway (well and the FETs)

Click to expand...

it definitely WILL matter. any inductance between the bulk capacity and mosfet will cause voltage spikes and kill mosfets like crazy if you switch fast. and you want to switch as fast as you can to lower your switching losses. i have seen voltage spikes on a bad layout as high as 100v with a 30v supply.

a voltage spike is induced with the following formula: Uspike = Di/Dt *Lstray

have a look at this: https://www.tf.uni-kiel.de/etit/LEA-download/dl-open/veroeff_2009/epe_muhlfeld.pdf
some more info: http://www.irf.com/product-info/igbt/pcb-layoutguidelines.pdf

this is actually why cheap controllers can get away with awful layout, as they switch super slow.

@wil

I really appreciate the drawing and detailed explanation. You did much better by hand than I ever could. I can see the advantages of your proposed layout. I can really shrink down board length in comparison to other layouts.

A tip from nieles's attached document

"Reduce the distance between the high side and low side IGBTs (I think this would apply to FETs too) to reduce the AC loop
inductance and to prevent damage to gate driver ICs."

This will still be something I consider for the high voltage version as long as I can mitigate ringing and voltage spikes well enough. Even the refereed document states that in-line configurations can be acceptable.


@nieles

I was under the impression that switching losses in FETs increase as switching frequency increases and conduction losses are more prominent in lower frequencies. See document linked below. This is why the more efficient buck/boost designs use larger components and have lower switching frequencies. Also, I'm thinking the switching frequency range for this VESC will be 20 to 30kHz as I'm only considering traction applications. I agree that low switching frequency allows for lower voltage spikes and therefore one can get away with a sloppier layout (like mine right now). The original idea i had for the HV layout was to run the high power supply and ground right on top of each other on the opposing layers and minimize loop area as much as possible. Still with the FETs all in a row though. Maybe I can still accomplish running the high current Vcc directly over ground with wil's general layout idea.

http://www.ti.com/lit/an/slyt664/slyt664.pdf

shaman said:

I was under the impression that switching losses in FETs increase as switching frequency increases and conduction losses are more prominent in lower frequencies. See document linked below. This is why the more efficient buck/boost designs use larger components and have lower switching frequencies. Also, I'm thinking the switching frequency range for this VESC will be 20 to 30kHz as I'm only considering traction applications. I agree that low switching frequency allows for lower voltage spikes and therefore one can get away with a sloppier layout (like mine right now). The original idea i had for the HV layout was to run the high power supply and ground right on top of each other on the opposing layers and minimize loop area as much as possible. Still with the FETs all in a row though. Maybe I can still accomplish running the high current Vcc directly over ground with wil's general layout idea.

http://www.ti.com/lit/an/slyt664/slyt664.pdf

Click to expand...

well increasing the switching frequency is one way for the switching losses to go up. there is more to the story. switching loss is defined on page 23 of the document you linked to. Psw = 2 * (Et1 + Et2) * Fsw. so if Fsw goes up switching losses go up. what i was talking about is the speed at which the mosfet is turned on and of. this is directly linked to the energy lost in Et1 and Et2. (see the document you linked to on page 23 for more info and diagram)

the switching speed is controlled by the gate resistors. the faster you switch the mosfet on and off the higher your Di/Dt will be, and the more voltage will be generated in the stray inductance. so this is why the cheap china controllers switch the fet on and off in like 1-2 microsecond. where you want to be at more like 300-500 nanosecond or even faster if your hardware can handle it. switching at an lower frequency doesn't lower the voltage spikes, only the switching losses will go down.

The original idea i had for the HV layout was to run the high power supply and ground right on top of each other on the opposing layers and minimize loop area as much as possible. Still with the FETs all in a row though. Maybe I can still accomplish running the high current Vcc directly over ground with wil's general layout idea.

Click to expand...

yes, thats the way to do it! this way the loop area is only the (length of track) * (thickness of pcb). A way to lower it even more is to use a thinner pcb or go multi layer and alternate between GND and VCC on every layer. so GND on even layer numbers and VCC on odd layer numbers.

@ nieles

I follow you now. Yes I am familiar with how hard or soft the MOSFET gates are being driven will affect rise time (on time) or whatever its called. I agree that faster is better since the MOSFET spends less time between fully on and fully off. This will also cause more ringing/spikes as you have mentioned. I do intend to tweak the DRV8353x smart drive features to balance all of this as best as I can.

Hi @shaman,

Been following this with interest. What are your rough timescales on this project? I would be happy to support your development through purchasing samples and testing, or helping you to select or procure components.

Also, is it possible to get hold of the BOM? Good to see you are using LCSC on the cost front!

clong said:

Hi @shaman,

Been following this with interest. What are your rough timescales on this project? I would be happy to support your development through purchasing samples and testing, or helping you to select or procure components.

Also, is it possible to get hold of the BOM? Good to see you are using LCSC on the cost front!

Click to expand...

I'm looking to have the Cheap VESC spinning a motor with results from the lab within a month. I just now got a board soldered up and I'm going through basic PCB debug at the moment. After getting the Cheap VESC functional and uploaded on GitHub, I will then redirect efforts to the 6 FET HV design. It's hard to estimate a schedule as I have intermittent military obligations and a full time job as a EE. I welcome any support yo have to offer! I have several people offering to help me test my design in their own applications but there's no way I can crank out so many of these by hand. Do you know of a practical way to have 5 or more of these boards assembled by a service that's not going to be crazy expensive? The BOM is just about done as I've been making minor tweaks to it throughout design. I've now got the BOM 100% sourced from LCSC except the parts that you can get for free as sample from TI. I still need to export the BOM into a file.

Project Update

Ordered and populated the damn 1.5V version of the linear regulator instead of the 3.3V by mistake. No ones fault but my own. I got through initial continuity checks and such, powered it up with a current limited supply at 12V 200ma, and got nothing. I traced power and found that Vcc was low at a perfect 1.5V. Already ordered the 3.3V version. Also found a string of components that weren't properly connected to ground even though Altium thought they were. I quick solder bridge fixed this and I fixed the problem in the design already. Thankfully it hasn't been anything catastrophic so far.

I grabbed a VESC 6 schematic from a thread somewhere and tried routing the power portion of it with TO220 FETs with the power rail layout I drew above and I think if you did end up using it or something similar you would easily be able to fit a 12 FET design into a 6 FET size aluminium extrusion box (125x35), even with the extra sensing components used on each phase. Inductance also wouldn't be worse, as you would keep the power entry location the same, but have your other 6 FETs on the other side (ie near the logic stage). It may be harder to avoid induced voltage spikes on your signal lines though.

I could NOT however work out any way to have FETs at the top and bottom while having the power rails on opposing sides of the board from one another, without going to > 2 board layers, or having awful power routing. It would be possible with some stacked GND VCC laminated bus bars but that wouldn't really be in the realm of $30 cheap we are talking about.




Excuse some strangeness to it, it's my first time in KiCad, normally I'm in Eagle. I couldn't work out how to do a copper fill area, I could only get it on the silkscreen layer, so the busses are just thick traces... and it's a KiCad v4 schematic imported to v5 so it's missing like half the package 3d models... anyway you can get the general idea from it.

You would also need a lot more capacitance to the power lines. You could get the power rails as close as your phase wire thickness if you eliminated the phase pad on the side of the board the rails run. This is kinda similar to https://endless-sphere.com/forums/viewtopic.php?f=30&t=55641, but on a PCB instead so you have the thin side of the bus bar, vs the thick side close to one another.

nieles said:

it definitely WILL matter. any inductance between the bulk capacity and mosfet will cause voltage spikes and kill mosfets like crazy if you switch fast. and you want to switch as fast as you can to lower your switching losses. i have seen voltage spikes on a bad layout as high as 100v with a 30v supply.

Click to expand...

I know you need capacitors as close to the FETs as possible to eliminate voltage spikes as much as possible from inductance (Which is huge on ebikes due to our long battery power cables.) I think in a top/bottom design you will be able to get both a large capacitor quite close to the FETs, and a smaller one right on the legs of it. I've got SMD caps in this design right on the legs, but you could definitely do a larger film cap instead. The low side caps are slightly further as they have to be after the current sensors > GND.

shaman said:

"Reduce the distance between the high side and low side IGBTs (I think this would apply to FETs too) to reduce the AC loop
inductance and to prevent damage to gate driver ICs."

Click to expand...

I didn't realise that the board inductance was treated separately vs the inductance of the motor and phase wires. I was under the impression that since our motor and wiring had such large inductances, the most you could really do is limit your on board resistance. Now actually thinking about it as 3 separate inductors I can see how it matters. Still I think with a design like this your inductance wouldn't be particularly worse vs side by side FETs. You can also add thickness since we aren't using surface mounted directFETs.

@wil

Great work in investigating this layout! I may even consider doing a separate 4 layer design just to try and make this happen. You don't have to wait on me though if you want to make this your own VESC variant!

Project Update

View attachment 3
Populated Board



Using wire as bus


using flat wire as bus

https://www.amazon.com/Solid-Copper-Bezel-Strip-Gauge/dp/B01F1FO9FU

Just wanted to show practical ways to beef up the high current traces. Easiest and cheapest is with the wire you already have for power and ground. Just bare the length of wire needed to cover the length of the trace, stick the wire through, lay the wire down and solder. The other technique is a cleaner, lower profile way using copper flat wire/bezel. It's relatively cheap(see link) and has enough copper mass to carry the current needed.Just cut to length and solder down.

I presume you have looked into using Seeedstudio, ALLPCB or other Chinese companies for prototyping? It's hard work using external companies, but if you are in the US I would guess your PCBA services are pretty expensive in low quantities? Are you in Altium or KiCad?

clong said:

I presume you have looked into using Seeedstudio, ALLPCB or other Chinese companies for prototyping? It's hard work using external companies, but if you are in the US I would guess your PCBA services are pretty expensive in low quantities? Are you in Altium or KiCad?

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Actually I just looked at https://www.7pcb.com/ and it doesn't seem like a bad deal. I still would have to front about $600 for 10 to 20 boards assembled. Maybe I could do a gofundme or something to help cover that. This Cheap version is in Altium but the future ones will be in KiCad.

shaman said:

clong said:

I presume you have looked into using Seeedstudio, ALLPCB or other Chinese companies for prototyping? It's hard work using external companies, but if you are in the US I would guess your PCBA services are pretty expensive in low quantities? Are you in Altium or KiCad?

Click to expand...

Actually I just looked at https://www.7pcb.com/ and it doesn't seem like a bad deal. I still would have to front about $600 for 10 to 20 boards assembled. Maybe I could do a gofundme or something to help cover that. This Cheap version is in Altium but the future ones will be in KiCad.

Click to expand...

I understand trying to go local to save on shipping time but it will probably work out a lot cheaper to wait a few extra days for a "production" run from a Chinese board fab house.

A lot of PCBA services don't source components themselves, you need to sort that out for them, or charge a fair bit extra to do so. I found the cheapest pretty much always came out to be Seeedstudio and using parts from their part libraries/the Shenzhen sourcing library as much as possible as that was almost the equivelent of buying in bulk due to them being shared between peoples orders.

Anyway a Gofundme or Kickstarter is definitely the way to go forward for your first run, you get the money before hand so you don't need to rely on people promising you money and never paying after the boards actually get fabbed. I'll chip in for one when you are at that stage.