OSHW TO247 IGBT watercooled laminated half-bridge

Lockout = preventing the adjacent side from tuning on if one side is active, i.e. when the high side is active, the low side is locked out from turning on.

Not sure why you need the logic gates myself or how they would interfere with the differential signal, but personally I would leave the driver chip do it's thing and not add them on.

In order to use differential signalling, you'll need to have a diode across the inputs of InHS+ and InHS- and another on InLS+ and InLS-, hook the cathode side to the + and the anode to the -; this will cause the diode to be reverse biased when the other side is commanded on. Took me a while to wrap my brain around how this worked until I simulated it and saw the magic in action.
 
the logic gates are there in HARDWARE external to uC because i do not trust software. once you get into the software wow.. that's a whole other world to develop what it means to have fault tolerant code. fault tolerant code, who even knows about this? and of those.. who knows how to actually do it? in my opininion, i have not even found proof yet that TI did it with their instaspin. they have good functional code and there is a TONNE of value in that, and its supposedly bug free, but fault tolerant? dunno. even if it where.. unless its been running 20 years you really don't know. and even if it has been running 20years.. still random things can happen, especially for space equipment because of photons penetrating non-rad hardened.. (big moose knows what i'm talking about), thankfully this last bit really doesn't apply to us, but could be as noise causing references to get weird causing software to produce weird stuff. anyway.. for 20cents in parts you avoid a failure mode that has potential of a fire. in the end, the hardware interlock is to protect against software error, be it your code had a flaw or be it is perfectly bug free yet external factors cause it to produce random crap.

i agree that the phase-leg gate drive IC i have in my schematic has this built in so you could argue i overdid it with the external logic gates, but i was not entirely sure i would end up using this phase leg gate drive IC or go back to independent.

deferentially driving signals is really for big power stuff, probably bigger than your standard EV. where your magnetic fields are intense, your noise floor is high, etc. like 80kW or higher system. you would put the differential driven signals after the hardware interlock but before the gate driver's input. its a power hungry approach. also same with fiber optics.. which is great for environments where noise immunity is the only way to survive, but fiber is power hungry approach.

i like how your hardware interlock has flag notification. you'll probably need to consider somehow to latch that because it will come and go perhaps faster than uC can pick it up. then what to do with this signal? in a real EV its not that big a deal to have a missing pulse every once in a while. actually this happens all the time intentionally for good fault tolerant code.
 
zombiess said:
you'll need to have a diode across the inputs of InHS+ and InHS- and another on InLS+ and InLS-
Okay, I need to find some extra inner peace to get that one. Will simulate.

the logic gates are there in HARDWARE external to uC because i do not trust software
Neither do I, its a bag of cats. I've seen rad hard fpgas running stress tests for months, tons of redundancy, cycle-by-cycle parity check of ram and wishbone buses, and the constant assumption that a stupid particle would flip a bit in your ram, or program counter if you have one. Its not pretty.

flag notification. you'll probably need to consider somehow to latch that because it will come and go perhaps faster than uC can pick it up.
About the logic... I think I'll remove it from this board and add it to the brain board, run high/low signals differentially from brain to gate. This way I can know and block PWM overlaps.
If the MCU sent a shoot through, it will be a pulse wider than a clock cycle so it must be able to read it back and trigger the ISR.
Gate driver will ignore any glitch shorter than 20ns, so there is a window between 20ns and the minimum IO time (50ns?) that I'm not particularly interested in detecting.

Also, having the logic in the brain I'm delaying the brain specs... because it might be easier to put a small fpga to monitor, just to assure firmware won't screw up, but that belongs to a future brain thread. I mean, 1 fpga chip rather than logic gates everywhere.
 
Neither do I, its a bag of cats. I've seen rad hard fpgas running stress tests for months, tons of redundancy, cycle-by-cycle parity check of ram and wishbone buses, and the constant assumption that a stupid particle would flip a bit in your ram, or program counter if you have one. Its not pretty.
exactly. noise won't do this but it does still ends in same result by different path potentially and the logic gate (or other hardware method) protects against that. its all of these types of failure modes that need to be thought out and build in a solution for (its a long list, ha!). by the time you're done it is surprising though to see end up with 20% more cost to accommodate all of it which to me is probably a cost you can justify quantitatively even at high volume production. its basically statistical at that point.. what is your MTBF, warranty etc. and you can just do the math to find the break even point. what i have found is adding the extra safety is always in your favour financially and obviously for other reasons too so to me it always was a no-brainer. but then i was not in a race to the bottom for $ so i dunno, it depends on the market you are targeting and the risk you can take with that market. i can not design for cheap, that is an art in itself that i have no experience with.

1 fpga chip rather than logic gates everywhere.
technically you'd probably use a CPLD for this but... now we splitting hairs.
 
technically you'd probably use a CPLD for this
Yup, he's right.

Thumbs up to wurth and texas instruments that sent free samples of the transformer and IC's. Saved me like 120usd in parts and shipping (its a 9000 km shipping)
I'm placing an order for the smaller passives and a couple of IGBTs. I want to check the performance of the power supply, voltage regulator, and start preparing double pulse testing for when I send the pcb to mfg.
I still lack current sensing for double pulse test, and the CNC needs maintenance before milling the DC bus.

3d board.png

The gate drive on the right looks ready for review. I added the option to make the power supply +-15v, in order to have a -2V to -14v span of negative gate drive to play with later. With a broken control input -VEE defaults to 2v (lowest overshoot), and regulator dissipation won't be a problem in that case.

I chose these fabulous gate resistors. If I use those R in all the gate driving its going to be something like 50usd per board just in gate resistors, so I'll give this some thought before committing.

Cheers!
 
Thumbs up to wurth and texas instruments
i don't have enough thumbs for TI.

gate resistor, 2W in a 1206 package? doubtful.. also, what is the inductance of thin film resistor? at your intended power level you might have to start thinking about non-inductive resistor. but nobody likes that cause its expensive, so make your board test and see how much ringing you get, if its a lot is probably cause of this. at the very least you should make a double footprint, 1206 + 2512. the 1206 is for the resistor you picked and the 2512 is for the CRCW thickfilm 1W rated. i don't know what the footprint is for SMD non-inductive, i only ever used TH non-inductive gate resistor.
+15V, -8V is good for 50kW drive using IGBT but the power dissipation is a lot here cause of the -8V, it adds 50% more so keep that in mind when you designing the gate driver power supply.

when you ready, if you want, send me your stackup, schematic and concept drawings i will review it for you
 
Since resistor inductance and wattage are possible issues, why not place 3 in parallel? Populate them all so the inductance drops and wattage dissipation increases. I like the 2512 footprint myself for its large surface area (thermal management). Of course this depends on space available, but the board looks sizeable. HighHopes suggested pulse rated non inductive resistors, but I could not justify the high cost of them for what I was doing.
 
2W per 1206 is certainly too good to be true, yesterday I emailed vishay so they can clarify how they performed the testing, and also if they know the inductance of those resistors, so I'm waiting for that.

AFAIK, SMD resistors are very low inductance because its a 2 dimension construction, there are no loops, thats why they are used so much in RF stuff. Some smd resistors are trimmed in such a way that they get some capacitance, but thats not a problem here.

I didn't believe those 2W either, so I put 4 of those 1206 as RgON, and another 4 as RgOFF. Thats 16Watts of magical resistance, and I wouldn't mind if its "only" 1W per 1206.
Having several 1206 is easier for me to try different R values, and they are laid out in such a way I can install one 2512 resistor in place of those four 1206 resistors. Vishay sells an equally magic 2512 6W resistor.

So lets wait for vishay response, I'd expect that the test was done with thick copper, or ceramic substrate, or aluminum pcb, or the chip is particularly effective to transfer heat from the thin layer to the pcb, or the resistor withstands much higher temps than common ones (not according to its datasheet though).

Wurth transformers arrived :)
 
lol
 
So here is how you get a 2W rating out of a 1206 resistor

image004.jpg

Its not magic, its a ton of copper area and filled vias around one resistor.
I'll make some space to place bigger resistors, 1206 won't work in this layout.

Vishay told me that inductance is not measured because its so low that its not considered important.

Also, I've been checking that this kicad project works on different computers, just in case. There are some missing 3d models that I must add to the repo.
 
That is funny right there. I wonder if the marketing department reviewed the datasheet and modified a few things to improve sales.

Reminds me of one of my favorite jokes:
“Milk production at a dairy farm was low, so a farmer wrote to the local university to ask for help. A multidisciplinary team of professors was assembled, headed by a theoretical physicist, and two weeks of intensive on-site investigation took place. The scholars then returned to the university, notebooks crammed with data, where the task of writing the report was left to the team leader. Shortly thereafter the physicist returned to the farm, and advised the farmer, “I have the solution, but it only works in the case of spherical cows in a vacuum.”
 
Its a bad move from vishay, they don't need to sell through cheap marketing bs. Sadly, its not that surpsing either, getting a real world spec out of an IGBT is like pulling teeth. Those 400A continuous at 25°for a TO247 is pretty much a spherical cow attached to an ideal, infinite heatsink.

I put 4x 2512 resistors for gate driving, still preparing the project for a review release of the gate driver layout.

Ti samples are still on transit for some reason my first order was cancelled and had to re-order it.
 
HighHopes, -and zombiess, and anyone willing to jump in-

this would be the stackup

stackup_smaller.png

The pcb project is here:
https://github.com/paltatech/half-bridge/archive/master.zip

I'd open it with a nightly build of kicad
http://downloads.kicad-pcb.org/windows/nightly/
instructions for ubuntu
http://kicad-pcb.org/download/ubuntu/

In the schematic, pressing "E" over a component shows its fields. I usually add a "mfg#" field with the part number of the component. Its not 100% complete and there might be some wrong parts, but it could help for checking datasheets, etc.
Layout is only partially done, in case I have to redo it. Ah, and the +-15 supply of the schematic is still +15/-8 in the layout until I get to test that circuit in the bench.
 
Phase copper sheet could be closer to the pcb (betweeh pcb and Vbus-), that way the DC bus inductance would be a bit smaller, but I think its better to leave the phase copper sheet away from the pcb so the electric fields generated by the phase dv/dt are shielded from the pcb by the other copper sheets...
 
How are you making the DC link capacitor connection to the copper bus and the power devices? I've always found this to be somewhat challenging. I have proper soldering tools that allow me to solder to thick copper bus, but this technique does not seem good for production. I'm interested to see what you have.

I don't have anything to add on the stack up, looks good to me.
 
zombiess said:
How are you making the DC link capacitor connection to the copper bus and the power devices? I've always found this to be somewhat challenging. I have proper soldering tools that allow me to solder to thick copper bus, but this technique does not seem good for production. I'm interested to see what you have.
I plan to weld the capacitor leads to the copper sheets

cap-bus interface.png

Imagine that the copper fingers are bent up and the capacitor leads are spot-welded to that finger. It could be a regular solder joint too. I'd try with a 0.8mm thick copper sheet and se how it goes.

3D modeling all of this is going to be a time consuming task. We have the cnc ready to try to mill the copper, but I think I'll test the power supply first.
 
my PCB stack up is the same. i'd try to keep phase out away from PCB because this is basically an uncoupled field, unlike the DC bus which is sandwitched together with its buddy. prefer to keep all these power copper pieces away from PCB though of course.

your cap to bus connection does not look viable at mid to high volume and a pain but doable at low volume with great care. in marketing speak this means you have a design weakness that if someone else did better (read cheaper and/or more reliably) you might lose competitive edge.
 
HighHopes said:
your cap to bus connection does not look viable at mid to high volume and a pain but doable at low volume with great care. in marketing speak this means you have a design weakness that if someone else did better (read cheaper and/or more reliably) you might lose competitive edge.
And its only doable if I get to think through all the steps and fixtures needed for a repeatable assembly. There is a fixture that hopefully holds the components and layers together in order to be soldered to the laminated bus bar. I'm not aiming at mid nor high volumes anyway.


Today I toyed with the idea of an assembly like this

assembly.png
The controller could be mounted on top of that metal sheet, shielded from the noisy stuff. The sheet would provide support for the green pcb.

No need to build the vey first controller like this (its hard to tweak and tune the board), but its good to have some general layout in mind.
 
Oh, and something important I forgot to add: I licensed the project under CERN open hardware license (OSL).

So, anyone can take the design files and modify them, but as soon as you distribute the modified hardware as a product, you have to make the new design files available for the community.

Its a bit restrictive, but its for a greater good
 
marcos said:
Oh, and something important I forgot to add: I licensed the project under CERN open hardware license (OSL).

+1
 
Folks, I'm slowing down this design for a couple of months, this thread sparked some interests to make the VESC controller of this inverter NOW, so since there is $ involved I'll put my time on the controller hardware design. That will take me a month, and then I have a 20 day trip, so.. 2 months.

I'll finish the power supply testing now though, because otherwise I'll flush the current progress from my bio-RAM and I'll have to start over again.

The controller is also fully open source, so I'll ask for suggestions here as well. Wish the VESC project good luck!

For some eye candy, this is how the gate driver board is looking now

 
Hey this is cool... A thread on ES that's exciting again :)

Lots of good info.

I have one question are you sure you want to wrap the gate signals around like that....?
I mean you have the driver on the 1 side of the gates why not keep the signals and resistors on the same side as the driver at least this will help the 1 side of each phase leg.

With laminated boards/system it might be ok anyways but it looks like a trace running parallel to the phase/HV and higher power stuff which will want to absorb the noise and mess with your gate control.
 
Arlo1 said:
Hey this is cool... A thread on ES that's exciting again :)

DIY is always the best reading :) Great to see another thread on hardware design.
 
Arlo1 said:
Hey this is cool... A thread on ES that's exciting again :)

Lots of good info.

I have one question are you sure you want to wrap the gate signals around like that....?
I mean you have the driver on the 1 side of the gates why not keep the signals and resistors on the same side as the driver at least this will help the 1 side of each phase leg.

With laminated boards/system it might be ok anyways but it looks like a trace running parallel to the phase/HV and higher power stuff which will want to absorb the noise and mess with your gate control.

Sorry, I don't follow what you said about signals and resistors and sides.

About a trace running parallel to the HV switching, yeah, I'm aware of that, and try to get them as far as possible. The main reason that I'm going this way is because these dudes have a similar setup in the front wheels that racked up like a bazillion miles, and their crazy CEO opened up their patents. http://www.freshpatents.com/-dt20160602ptan20160157374.php

Here is a sneak peak at the brain of this board I've been working on. I assembled 3 of those and they are ready to spin a motor in my bench. The controller will have its own thread soon enough.

file.php
 

Attachments

  • with integrated controller.png
    with integrated controller.png
    76.1 KB · Views: 3,377
Back
Top