Odd# of mosfets vs even#

John in CR

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I have a wide range of controllers, 6-9-12-15-18fet, and soon a big 24fet controller. I understand that each phase has it's own bank of fets, but I'm unclear what the different fets do in each phase. The little 6 fet controller seems to have 1 for input and one for output, and the even numbered controllers all have the same kind of balance. The odd number of fet controllers appear to have the extra fet as extra output for each phase. Since the phase current going out can be so much higher, that's where sharing the load between more fets would seem to be more beneficial. This begs the question, is a 12 fet controller really any better than a 9 fet, is an 18 fet controller really any better than a 15 fet, etc?

John
 
I don't recall the reason John but Luke has told me in the past that even number of fets in the controller is preferable.
I tried to find the PM to see the reason Luke gave but wasn't successful.

KiM
 
A 9-FET controller would generally have 1 high-side FET and 2 low-side FETs per phase.

There is some benefit to this arrangement, particularly at low duty cycles where current is freewheeling a large portion of the time. In some situations under low duty-cycles a 9-FET might actually be slightly better than a 12-FET. Since the high-side FETs only conduct for a small portion of the time, switching losses are pretty important, and the gate driver can switch 1 FET faster than 2 reducing this loss. At higher duty cycles the lower Rdson of 2 parallel FETs is more advantageous than the fast switching so the 12-FET is better here.

If the controller was set up for synchronous rectification, the 9-FET would have more of an advantage, since it could take advantage of the 2 low-side FETs to reduce Rdson and have lower loss. With regular freewheeling, the only benefit is splitting the heat between 2 FETs instead of 1.

So, I guess the answer is that an odd-number controller would probably have some advantage at lower duty cycles (and during current limiting) but the even-number should prove better under WOT. Overall, you probably come out ahead with the even-number but in some cases you can save a few bucks with 3 fewer FETs and do just fine.
 
rhitee05 said:
Since the high-side FETs only conduct for a small portion of the time, switching losses are pretty important, and the gate driver can switch 1 FET faster than 2 reducing this loss.

I checked this out on my scope, and the 6fet infinion and the 18fet infinion, and neither of them had and difference in the gate drive signal at all when i added up to 6 fets of gate load to the output. It also seems to have identical output between the 6fet and 18fet. The gate resistors are high enough it just doesnt make an observable difference in the gate driver waveform (at least for these infinions).

The RdsOn loss is the big one. Running an even number of FETs makes this as good as its going to get.

IMO, a 9fet is a marginal advantage over a 6fet, and a 15fet a marginal advantage over a 12 fet. They would share clamping the freewheeling over a little wider area, and have a little less heat generated, but in our controllers built around TO220 fets, the package limits of the top side fet are going to be the real limiting factor in performance, and you dont remedy that until you move up to the next multiple of 6fets.


My $0.02
 
I'll add one or two advantages of adding an extra low side FET that hasn't been mentioned above by Luke and rhitee05.

First point is lower losses during regen braking. During regular driving the low side FETs on these controllers are just used as diodes, so paralleling them will not help much with efficiency (although it will help with reliability by dividing the freewheel current into an extra device... see bellow). However, during regen it's now the bottom FETs that are being actively switched, and usually at a pretty low duty cycle so they are conducting a long period of time compared to the top FETs. So having an extra low side FET will help regen be more efficient (less heat) and more reliable.

Another advantage to an extra low side FET is low duty cycle robustness of the controller. Both top and bottom FETs conduct the same phase current during each PWM cycle, but at low duty cycles the bottom FET's diodes are clamping this current for a much longer time than the top FETs are conducting. Not really any efficiency advantage in this case, but having an extra low side device to handle the relatively long duration freewheel current will help reliability at partial duty cycle when phase currents are usually greatest.

Oh!... one other thing I almost forgot, and is actually the most important advantage of them all. We are all only thinking about the single PWM'd phase in this discussion... but there is always the other phase being held low (batt-) that we have to think about too! Reducing the ON state resistance of the low side FETs will help here with both controller efficiency and robustness.

Pat
 
liveforphysics said:
I checked this out on my scope, and the 6fet infinion and the 18fet infinion, and neither of them had and difference in the gate drive signal at all when i added up to 6 fets of gate load to the output. It also seems to have identical output between the 6fet and 18fet. The gate resistors are high enough it just doesnt make an observable difference in the gate driver waveform (at least for these infinions).

That's interesting, because the switching time should increase with more FETs. Whatever the driver setup, it can deliver a certain peak current, so if it needs to deliver 2x as much charge to 2 FETs, it should take twice as long. I don't know anything about the gate drive circuits the Infineons use, so there may be something going on I don't know about. I assume you're looking at a low enough time-scale on the 'scope that you can see the gate voltage rise (probably ~1us or so, I think others have said?)? I also assume you're measuring at the FET gate itself, not on the upstream side of the gate resistor. If true, that would seem to reduce the advantage of the odd-FET significantly.

You might find this document interesting:
http://www.analogzone.com/pwrt1208.pdf
It's pretty technical, but it discusses in very great detail the high- and low-side FET losses (although they assume synchronous rectification) and the efficiency trade-offs for each one.
 
These guys have a 20ohm resistor, and switch ~10v (i dont remember exactly). ****EDIT I was totally 100% wrong here, somehow confused the RC controller FET design with the infinion design...Ooops! The infinion boards tie all the gates common, and use an up-stream gate drive resistor***

It's half an amp of load per FET for the first nano-second of switching, then tapers to zero amps. (then bounces current back into the gate drive rail, oscillates a bit a few times etc etc, as you know of course).

I will go double check the 6fet, 12fet, 18fet and 24fet boards I've got sitting here, but I think they all used the exact same FET driver, which is a 3amp unit if I'm remember reading the specs correctly, which unless I'm seeing something incorrectly on the scope and from the numbers, means no noticeable difference in switching performance until you go do a 36fet controller or so, but perhaps I'm seeing something wrong?

***Edit*** Corrected, the infinions all use the same SMT zenner clamping diode called "T4"

The infinions are way different than the RC controller FET stages... lol This is what they use.
The 24fet model uses an external SMT gate drive mosfet for each channel labeled "Y6" for the highside FETs, and one labeled "Y1" for the low side fets.
The 18fet model uses an external SMT gate drive mosfet for each channel labeled "1HD" for the top and bottom.
The 12fet model uses an external SMt gate drive mosfet for each channel labeled "Y2" for highside FETs, and one labeled "Y1" for the low side fets.
I don't have a 6fet in an easy to disassemble way handy right now to check it.
 
All I know is that these 15 fet 60v30a Infineon controllers rock with the matched motor. I've been running at 74v nominal and I just reconfigured the 3 legged shunt of one to 30-40% of its stock setup. Running a 20" tire and this modded controller vs the 23.5" tire Luke and I used with the Methods 18fet 100v100a controller is a close match in performance. The big controller was giving more pull off the line, but in the 30-50 mph range I think the stock controller and smaller tire wins. I still need to test it on some steeper hills, but if it holds up it's perfect for my daily rider. I can't wait to try 2 of them on the performance build I'm trying to get finished. :mrgreen:

John
 
Okay, trying to make sure I understand. Each FET bank has a single driver chip with 20 ohm series resistor and then connected to 1-4 gates in parallel. The chips have different labels, but that might not mean very much. Could be a different part, or could just be different lot codes. I assume they all look the same (same package). On the gate side of the series resistor there's a Zener diode. Probably a 15V Zener or something like that to make sure the gates don't blow up during oscillation (max voltage 20V).

If the driver voltage is around 10V, then there will be about 1/2A peak through the resistor as you said. But then they would have to switch at different rates. 6-FET would be 1/2A per FET, 12-FET would be 1/4A per, etc. It just doesn't seem to obey the laws if the switching times do not change. Not saying you're wrong, I just don't see how it's possible.

I don't suppose you have the ability to capture a 'scope plot of one of the switching transients and post it? The best thing to see would be the gate-to-source voltage of one FET and the voltage across the series resistor. On the same plot if you have two probes, two plots otherwise.

The Vgs curve should look something like the topmost plot in this figure (shamelessly borrowed from TI). The resistor voltage (i.e. gate current) should look like the second one down. The important time interval is from when Vgs passes Vth to the end of the flat region (the Miller Plateau), this is where the switching loss occurs. The final slope up to the full 10V is not as important - the MOSFET is already on, just being fully "enhanced" to minimum Rdson. Vth for a 4110 FET is approximately 3V.
 
sorry if i misunderstand, but are you saying each driver has 1amp or more going through it?? I think the current would be tiny tiny tiny, the whole board only draws 65mA or something like that.
 
The better gate drivers can push 3A+ for switching, but keep in mind this is for a very brief time period. Less than 1% of the time. That makes the average current draw still fairly small.
 
what the: 3amp? must be a very very short time period, mS or nS?
Seems conterintuitive: a 65mA source current, can provide 3amp even for a brief period? this is something completely new to me, nontheless very interesting indeed. I'm guessing this is similar in principle to the continuous (average) current, and pulsed current found in xie cheng programming interface?
 
You stick a little cap there feeding the gate driver FET.

I got some 7amp, and now 15amp FET driver's from Maxium, but both types are low-side... I need some high current non-boostrapping type high-side drivers...
 
I like this little guy:

http://www.national.com/pf/LM/LM5112.html

It's a cheap little single driver capable of 7A. Bootstrapping one to drive the high-side is easy, you just need a diode, capacitor, resistor, and maybe a zener (not absolutely req'd). Then it's just a matter of driving the input logic: optos, cap-coupled line, etc. Not quite as easy as a packaged half-bridge driver, but most of those max out at 3A or so.
 
Another consideration is in most controllers, the low side FETs are only switching at the commutation frequency, not the PWM frequency. Only the high side is switched with the PWM. Since the switching frequency will be way lower, you can have additional devices in parallel without introducing much additional switching loss.
 
Okay, so the idea of having more lower side fets is to spread the freewheeling loss heat out more? Is that right?

But isn't paralleled diodes a bad idea due to current hogging? Or is that more than offset by the ample heat dissipation between the mosfets(Through the heatsink) so it's not a concern?
 
rhitee05 said:
I like this little guy:

http://www.national.com/pf/LM/LM5112.html

It's a cheap little single driver capable of 7A. Bootstrapping one to drive the high-side is easy, you just need a diode, capacitor, resistor, and maybe a zener (not absolutely req'd). Then it's just a matter of driving the input logic: optos, cap-coupled line, etc. Not quite as easy as a packaged half-bridge driver, but most of those max out at 3A or so.

Beautiful!

I think I'm starting to more widely see the beauty of opto-isolation. If you blow the mosfets, you don't risk the logic circuitry. The prorogation delay and rise time seems like it could complicate it, though. Maybe not.
 
swbluto said:
Okay, so the idea of having more lower side fets is to spread the freewheeling loss heat out more? Is that right?

But isn't paralleled diodes a bad idea due to current hogging? Or is that more than offset by the ample heat dissipation between the mosfets(Through the heatsink) so it's not a concern?
Fechter is not talking about freewheeling currents of the low side FETs on the PWM phase, but rather about the other phase that is always held low (batt-) for the whole commutation time. I had actually already mentioned this point on the previous page of this thread, but no one responded to the post for some reason... it probably sounded more like chinese than english to most people I guess.

Anyways, I hope you included this extra low side commutation loss in your calculator, and maybe also add the diode recovery time too for the low side FETs on the PWM'd phase.
 
ZapPat said:
swbluto said:
Okay, so the idea of having more lower side fets is to spread the freewheeling loss heat out more? Is that right?

But isn't paralleled diodes a bad idea due to current hogging? Or is that more than offset by the ample heat dissipation between the mosfets(Through the heatsink) so it's not a concern?
Fechter is not talking about freewheeling currents of the low side FETs on the PWM phase, but rather about the other phase that is always held low (batt-) for the whole commutation time. I had actually already mentioned this point on the previous page of this thread, but no one responded to the post for some reason... it probably sounded more like chinese than english to most people I guess.

Anyways, I hope you included this extra low side commutation loss in your calculator, and maybe also add the diode recovery time too for the low side FETs on the PWM'd phase.



Do you have any relevant equations? It's possible we're thinking of the same thing, but aren't calling it the same thing. So far, mosfet resistance, switching losses and freewheel losses are accounted for. If there's any other significant ones that you feel weren't included, it'd be helpful if it had a distinct name so I could google-research it more easily.

http://en.wikipedia.org/wiki/Buck_converter

Switching losses
25d01a3e4d75e92e7f36f5cff7263b54.png


diode(from same source):
PBODYDIODE = V_F * I_o * t_NO * f_SW

What do you think a typical value for t_NO, the non-overlap time, is? And what do you think a typical forward voltage is? .9? 1.3?

Reading that section, it appears that isn't the same as the "free wheeling losses" whose power equation is mentioned below.

Freewheeling:
PD = VD(1 − D)Io

They also have another equation for the gate circuit drive:

PGATEDRIVE = QG*VGS*fSW

Do you think the gate drive is that significant? I mean... do you think it's what's causing the mosfets to blow from getting too hot? It seems a 4110 has a QG of 150.0 nC (nano-coulomb's, right?) so a typical gate loss might be 150 * 10^-9 * 12 * 10,000 = 9/500 watts or .018 watts. When the switching and resistive losses are like 20+ watts... I'm thinking it doesn't matter much.
 
I'm not actually talking about the phase doing the PWM (working as a buck converter), but the second phase that is being weld to ground through the low side FETs, so that the current can circulate through two motor phase arms at a time. Losses would be the simple conduction losses of the low side FETs for this second phase, and has to be added to all the buck converter losses of the first phase.
 
ZapPat said:
I'm not actually talking about the phase doing the PWM (working as a buck converter), but the second phase that is being weld to ground through the low side FETs, so that the current can circulate through two motor phase arms at a time. Losses would be the simple conduction losses of the low side FETs for this second phase, and has to be added to all the buck converter losses of the first phase.

Is this "conduction" loss a diode-esque or ohmic loss (I think you mentioned diode, but just want to make sure you're not talking of the FET's resistive loss.)? Do you know what a typical magnitude is? I can see the formulas aren't coming by too handily, so it looks like I'll have to create it.


So, correct my understand if needed, but there's the high side mosfet and low side mosfet that's both "ON" when the two phases commutate. I was under the impression both mosfets endured resistive losses during the ON portion, but you're saying the low portion is ALSO encountering diode-esque conduction losses as well? Or it's ONLY encountering diode-esque conduction losses? Does the low side ever encounter purely resistive losses?

So far, it's sounding like

D * V_F * I_0

Where D is the duty cycle between 0 and 1.

EDIT:

After correcting the functions, it appears I just had to add a duty cycle factor to the resistive losses. Which means, the new formulas just reduce the predicted resistive heat. Better to have a "pessimistic estimate" than an "optimistic" one. :mrgreen:
 
There are be a total of 3 FET banks which are involved at any given time. Two are switched on by the commutation, usually with the high-side PWMing and the low side held steady on, and the third is involved due to freewheeling (or synch. rectification if implemented). Each sees a different loss:

- One of the three high-side FETs will be seeing switching losses due to PWM, and resistive losses based on the duty cycle on-time.
- The complementary low-side FET will be seeing freewheeling diode losses based on the duty cycle off-time.
- One of the other two low-side FETs will be seeing resistive losses 100% of the time.

Say the current commutation state is A+ and C-. The high-side A FET sees switching + resistive loss*D, the low-side A FET sees freewheeling loss*(1-D), and the low-side C FET sees resistive loss (100% duty).

The sum of those three losses is equal to the total controller heat output (neglecting small contributions). Each bank of high-side FETs will see an average loss of (switching + resistive*D)/3, since the commutation is rotating. Each low-side bank sees an average loss of (freewheeling*(1-D) + resistive)/3. It should be immediately obvious that the low-side losses will always average higher, except for the case D=1, thus the advantage of having an extra FET to share the load here.
 
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