glenn0010
100 W
Hi all,
I am doing my final year thesis in electronics and control. I have built a prototype board for my BLDC motor controller. The board has a lot of test points and jumpers so I can manipulate components in and out of circuit to see what effect they have on the wave forms.
What I want to test for now is:
1. The effect of the electrolytic capacitor in parallel with the ceramic bootstrap capacitor.
2. The effect of the diode in parallel with the gate resistor
3. Effective Snubbing to have clean 'power' wave froms
Below are the schematics:
And here is my soldered board:
I tested the functionality of all the FETs using a 10 Ohm load resistor. I put the probes across the load resistor and here are the waveforms I got:
I measured the ringing frequency at around 13.2 MHz. I obviously want to eliminate this ringing and that nasty voltage spike. My FETs V[sub]DS[/sub] is rated at 100V however I want to eliminate this.
I have read several papers and application notes on Snubbing and from what I understood and from the equations it seems that the voltage spike and ringing is to do with the stray inductances of the components traces etc (L[sub]LK[/sub]).
I have used this AN from NXP as my main guide. https://assets.nexperia.com/documents/application-note/AN11160.pdf
I do have some questions though:
1.Do I just need an RC snubber circuit across the high side FETS as the NXP AN seems to State?
As this document from TI seems to inidcate that the RC snubber should be placed across the low side FETs : http://www.ti.com/product/CSD88599Q5DC/datasheet/layout?
An I have found this source that indicates snubbers across both sides
2.Could I get away with placing just 3 ceramic caps across each half bridge as I just have big fat electrolytics across the POWER rail which are useless for this kind of thing.?
Sorry for the questions but I am a bit confused.
I am doing my final year thesis in electronics and control. I have built a prototype board for my BLDC motor controller. The board has a lot of test points and jumpers so I can manipulate components in and out of circuit to see what effect they have on the wave forms.
What I want to test for now is:
1. The effect of the electrolytic capacitor in parallel with the ceramic bootstrap capacitor.
2. The effect of the diode in parallel with the gate resistor
3. Effective Snubbing to have clean 'power' wave froms
Below are the schematics:


And here is my soldered board:

I tested the functionality of all the FETs using a 10 Ohm load resistor. I put the probes across the load resistor and here are the waveforms I got:


I measured the ringing frequency at around 13.2 MHz. I obviously want to eliminate this ringing and that nasty voltage spike. My FETs V[sub]DS[/sub] is rated at 100V however I want to eliminate this.
I have read several papers and application notes on Snubbing and from what I understood and from the equations it seems that the voltage spike and ringing is to do with the stray inductances of the components traces etc (L[sub]LK[/sub]).
I have used this AN from NXP as my main guide. https://assets.nexperia.com/documents/application-note/AN11160.pdf
I do have some questions though:
1.Do I just need an RC snubber circuit across the high side FETS as the NXP AN seems to State?
As this document from TI seems to inidcate that the RC snubber should be placed across the low side FETs : http://www.ti.com/product/CSD88599Q5DC/datasheet/layout?
An I have found this source that indicates snubbers across both sides

2.Could I get away with placing just 3 ceramic caps across each half bridge as I just have big fat electrolytics across the POWER rail which are useless for this kind of thing.?
Sorry for the questions but I am a bit confused.