Custom controller-toy - how to get rid of these bounces?

I've been playing around developing a "toy controller" to gain experience to jump to higher dreams later on. This controller is an h-bridge for a 250W dc-brushed motor. I developed the whole thing from the ground up and assembled the first prototype in a perf-board (I know, not such a good choice, but is part of the learning path anyway; 2nd prototype will have a custom PCB). The bridge uses both N and P MOSFETs; only the N-MOSFETs do PWM switching. Which half-bridge has 2 N-MOSFETs paralleled with 10 Ohm gate resistors and 1 P-MOSFET.

I started by testing with a car lamp and then a small DC-motor from a wireless vacuum cleaner. What I'm showing below doesn't change with being the lamp or motor, with current nor with more capacitance at the power rails. This is what I see at the input of the N-MOSFETs driver and at the N-MOSFET's drain (load: 21W 12Vcar lamp):



The MOSFETs are ON when the yellow line is low. Directly at one of the N-MOSFETs gate I see this:



The PWM frequency is 10KHz and the duty cycle on these pics is very very small (some 2%; that's how I'm limiting current while not implemented in the firmware).

From where exactly are these bounces coming from? This is where the MOSFETs turn on/off. I have 35cm thick long wires from battery (2 series gel lead-acid 7Ah) to controller, another 20cm from controller to load. I see this with currents from 1A to 12A or 13A, current changes very little the effect. Circuit routing is not good, I have some thick 5 - 6cm wires to distribute power to the half-bridges, I have also a shunt on the GND line, from GND to the N-MOSFETs' source; don't know exactly the value but should be some 6-7 mOhm max. Are the drivers too fast? I see the same bouncing on the GND line. What's your opinion?

Update: Here's the schematics of the power section, just one half-bridge, the full circuit has 2 of these and an extra micro-controller based circuit as brain. Pins from the micro-controller (AVR) connect directly to HB1_L (scope yellow traces are taken here) and HB1_H. MGND is GND through the shunt. The blue trace on the 1st waveform was taken at HB1_OUT (only HB1_L taking the PWM, and the P-MOSFET on the other half-bridge is constantly on).

Do you have a schematic of your circuit? That would make it more helpful to see what's going on.

I've just updated the main post with the schematics, thanks!

update: just did a minor change on the schematics to reflect reality 100%

Guys, no ideas ?... Is there a more adequate sub-forum or even forum to discuss this? Thanks!

Well, hard to be certain but I would definitely expect the non-ideal layout of the circuit to have some effects. I can't be sure what the time scale of your scope plots is, but if I read 200 ns/div correctly it looks around 800 ns. That's moderately fast, probably about as fast as you could expect for a layout with a lot of inductance like yours. The basic shape of the gate voltage waveforms looks right. You should expect to see a ramp upwards, then a flat plateau , then a final slope upwards to full voltage. The plateau is caused by the drain voltage is changing, which is what I see in those plots. The spikes and over-shoot are probably inductive effects. Here's what the switching sequence of the FET looks like. As the gate voltage starts to rise, nothing happens until it hits the threshold level which is about 3V for your FETs. At this point current begins to flow but the drain-source voltage is constant, and the gate voltage continues climbing. Once the drain current levels out, the drain-source voltage begins to decrease. This causes current to flow through the parasitic gate-drain capacitance in the FET, which in turn causes the gate voltage to plateau. Once the drain-source voltage is near zero the plateau ends and the gate voltage begins climbing again. At this point the FET is "on" and the rising gate voltage only decreases the Rdson to the fully enhanced value.

I'm curious why you've chosen to use P-channel FETs in your bridge? Those usually have much higher Rdson than N-channel FETs so they are rarely used. I know you're not going for high-power here, but you wouldn't be able to with a P-channel. You could use a pair of N-channel FETs and drive them with a half-bridge driver chip and have a much simpler circuit than your discrete driver.

800ns? I guess you're measuring the the "on" part of the cycle at the drain. The raise/fall times at the drain are near 200ns. Yes, the plots are all 200ns/div except the lower half of the 2nd one which is 100ns/div. I would say the MOSFET thresholds are about 4V; in the 2 plot each vertical division is 2V (because the screen is divided in 2 vertically, the division is not square, it has half the height).

I used P-MOSFETs because it was simpler. I could get my hands on these MOSFETs and on the discretes much more easily than at MOSFET driver chips. I admit I also like analog design. These P-channels have 20 mOhm spec'ed RdsON (pretty good for P's as far as I've seen) which means some 2W - 2.5W dissipation at max continuous current (they aren't switching PWM) which seemed acceptable to me.

I understand the general form of the waveforms. My problem is with that "oscillation" when the gate reaches the plateau. Specifically, this is propagating into the microcontroller part and "disturbing" it a bit, by causing it's power to raise almost 1V. I'm still not able to fully explain this, because the microcontroller is being powered by an independent set of batteries. The bounce can be seen in the yellow trace, which is the microcontroller pin. If the bounce was on the GND, it should not be seen at the pin because GND's are connected and the microcontroller's Vcc is relative to GND... or am I missing something?

I want to do a 48V-60V 350A DC-brushed controller next and this is training

Njay said:

800ns? I guess you're measuring the the "on" part of the cycle at the drain. The raise/fall times at the drain are near 200ns. Yes, the plots are all 200ns/div except the lower half of the 2nd one which is 100ns/div. I would say the MOSFET thresholds are about 4V; in the 2 plot each vertical division is 2V (because the screen is divided in 2 vertically, the division is not square, it has half the height).

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In that case, the switching is much faster than I thought. It appears that the actual switching period is something like 250-300 ns, that is only the portion from when the current starts flowing to when the voltage reaches saturation, not counting the very early and very late portions. That's very fast.

The spec for the MOSFET threshold is between 2V and 4V, with 3V as the nominal. You might think it's higher from the graph, but keep in mind that current starts flowing before the voltage changes, so the threshold voltage is reached before you see the drain voltage change. You'd need to look at the current to see exactly when.

A good start might be to increase the value of your gate resistors to slow the switching time. 300 ns switching time is almost certainly too fast for the sort of circuit you've built here. I'd suggest doubling or even tripling the value, a switching time of 1 us would probably be good. You want faster switching with higher power, but for something like this you're better off slowing it down so the circuit behaves better. There are a lot of inductive effects that could be triggered by the faster switching and causing the issue you're seeing. If you increase the gate resistors and they don't go away, then it's time to dig deeper.

Njay said:

I want to do a 48V-60V 350A DC-brushed controller next and this is training

Click to expand...

I would strongly suggest you switch to a more standard all-N FET bridge when you get to this point. Not that P-FETs wouldn't work, but I think it would be easier.

rhitee05 said:

The spec for the MOSFET threshold is between 2V and 4V, with 3V as the nominal. You might think it's higher from the graph, but keep in mind that current starts flowing before the voltage changes, so the threshold voltage is reached before you see the drain voltage change. You'd need to look at the current to see exactly when.

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Ok...

rhitee05 said:

A good start might be to increase the value of your gate resistors to slow the switching time. (...)

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Ok, thanks, I'll try just that and let's see what happens.

rhitee05 said:

Njay said:

I want to do a 48V-60V 350A DC-brushed controller next and this is training

Click to expand...

I would strongly suggest you switch to a more standard all-N FET bridge when you get to this point. Not that P-FETs wouldn't work, but I think it would be easier.

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Of course ! I'll use only N-MOSFETs in one of the big TO packages, symmetrically placed around the half-bridge's output on the heatsink. It would be very difficult to use P-MOSFETs for such current.

You don't need to worry about trying to measure the threshold voltage or really much about how the switching happens. I just wanted to explain in case you were interested. Understanding the switching process will help you squeeze out more performance if you're so inclined.

Slowing the switching is generally very helpful to make the controller behave nicely. Everything just gets a lot harder the faster you want it to switch. Better to start really slow, then you can gradually speed it up as you observe and fix the problems that come up. Eventually you'll reach a balance between the performance you want and the effort you're willing to expend.

rhitee05 said:

You don't need to worry about trying to measure the threshold voltage or really much about how the switching happens.

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Indeed I'm not . But I like to measure these things because I've never seen it before; the graphs in the books are nice but reality is always more complicated. I'll try to measure the gate current with and gate voltage, now got curious about it; and I also still don't know exactly how much current the drivers ended up being able to sink/source.

rhitee05 said:

I just wanted to explain in case you were interested.

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I am!

rhitee05 said:

Understanding the switching process will help you squeeze out more performance if you're so inclined.

Slowing the switching is generally very helpful to make the controller behave nicely. Everything just gets a lot harder the faster you want it to switch. Better to start really slow, then you can gradually speed it up as you observe and fix the problems that come up. Eventually you'll reach a balance between the performance you want and the effort you're willing to expend.

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As far as I've learn so far, switching speed is a game between optimizing dissipated power, electromagnetic emissions, "driver power" and current limiting response time, of which you can choose to have *almost* all of them at the same time (typical engineering problem ). I chose to design fast drivers above all the others, mainly with minimizing power dissipation in mind, but also because an intrinsically fast driver can be turned into a slow driver the way you already mentioned but not the other way around. I totally agree with you on the "start slow and then speed up" and I usually follow that philosophy but I got a bit in a hurry.

The prototype is a bit hard to change (did it in veroboard and added some corrections which complicated it further) but I'm going to start designing the 2nd version on a PCB and it will be easier to try things on. Besides these bounces, the other problem I need to solve is thermal management, which, if I didn't fail to solve, I'm on the success/fail border. This time the (re)design of the entire controller will start by the heatsink and then the rest will fit in around. Another good lesson from this project.

Njay said:

As far as I've learn so far, switching speed is a game between optimizing dissipated power, electromagnetic emissions, "driver power" and current limiting response time, of which you can choose to have *almost* all of them at the same time (typical engineering problem ).

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Don't forget about issues such as the bounce on your drivers. If you want to be technical, that rightly falls under the same "electromagnetic compatibility" heading as EMI, but most people think of them as two distinct issues. Either way it's a tradeoff along with the other factors.

Njay said:

The prototype is a bit hard to change (did it in veroboard and added some corrections which complicated it further) but I'm going to start designing the 2nd version on a PCB and it will be easier to try things on. Besides these bounces, the other problem I need to solve is thermal management, which, if I didn't fail to solve, I'm on the success/fail border. This time the (re)design of the entire controller will start by the heatsink and then the rest will fit in around. Another good lesson from this project.

Click to expand...

I have a lot of ideas in my head for controller designs, which unfortunately I have neither the time or money to pursue at the moment, but in all cases I consider the thermal and electrical layout problems the main design challenges. Personally, my approach is to start by considering both the thermal design and the high-current paths simultaneously. If you want to work on fast switching (which I agree is a very useful goal), then the right place to focus your energy is on laying out very low-inductance paths for the high-current loops. This includes the gate drive, the main decoupling cap bank, and the stray inductances at the FET packages. If you can't keep those under control, then you'll always need to slow the switching down to compensate. Since reducing the switching time also reduces the losses, I think it makes sense to prioritize that at the same level as the heatsink. After those two are done, the rest is relatively cake.

Also, there tends to be a bit of a tradeoff as the inductance requirement wants the FETs to be close together but thermal design tends to want to spread them out.

You're absolutely right about joining the high current path design to the mechanical design of thermal management. Paths need to be short and MOSFETs need to be positioned well relative to the cap bank, bus bars and drivers, all in a way that is, also, mechanically rugged. For my future "big" controller I think I can get away by paralleling just 4 TO-247 MOSFETs, IRFP4368 or similar (I'll use only some 100A-125A continuous; 200A-250A for a minute or so). For this one I'll do more serious calculations on dissipation. I have one sketch with a square "1st level" heatsink, with a MOSFET on each corner and output connection at the center of the heatsink. Here's an idea, we should create a topic on power stage design proposals

There's a lot of good information about controller design and challenges on the net, but very spread out. I'm also thinking about gathering all of this good stuff in one place.

rhitee05 said:

Also, there tends to be a bit of a tradeoff as the inductance requirement wants the FETs to be close together but thermal design tends to want to spread them out.

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I think that could be solved easily by ingenious design of the heatsink, at the expense of having a very very custom heatsink with all difficulties coming from that.

The 4368 FETs are a good choice and the TO-247 package is far superior to the little -220s. Four of those in parallel is probably overkill if your spec is 125A continuous/250A peak, but you know your design criteria better than I do and probably haven't looked in that much detail anyhow. The trouble with large parallel arrays is that layout becomes a real pain, gate drive is tricky, and current sharing is never perfect. When you get to that point, you might see if 2x or 3x will get you where you need to be. I think it's a good tradeoff to use a smaller number of FETs to simplify the electrical design, then take that saved effort and put it into making the thermal side better to deal with the higher loss. 2x of those would definitely be capable of meeting your specs if the thermal solution is good enough.

Personally, my choice for the controller I hope to design someday is the IRFS3006-7. The SMT package and multiple source leads make it perfect for a really clean, low-inductance layout. SMT makes the thermal design more challenging, but I have a couple ideas that I think will take care of it. Probably not suitable for really big power, but should be ideal for a moderate setup.

I don't think I would need it for my planned design, but if I did want to go higher-power I would probably make the leap to water-cooling. That lets you deal with so much higher power density, so the FETs can be closer together and you can use fewer of them. I think you could easily design a 200A continuous controller using 2x paralleled 3006-7's with water cooling.

rhitee05 said:

The 4368 FETs are a good choice and the TO-247 package is far superior to the little -220s. Four of those in parallel is probably overkill if your spec is 125A continuous/250A peak, but you know your design criteria better than I do and probably haven't looked in that much detail anyhow.

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There are several reasons for me to design with a good margin. At 1st I'll be limited by the current my LiFePO4 batteries can handle while maximizing their life (at their price, I'm investing, really, not just "buying"), but in the future I may invest in something "better". Then, for one single, custom unit, one more MOSFET isn't going to increase the cost dramatically; not counting cents for mass production. I prefer to do something I can still use after battery/motor upgrade (this is for a motorcycle) and have things running cold and efficiently. In this case I rather avoid the heat in the 1st place than having to deal with it. Forced motor cooling is also in the road for the future, allowing me to use more current during more time.

rhitee05 said:

The trouble with large parallel arrays is that layout becomes a real pain, gate drive is tricky, and current sharing is never perfect. When you get to that point, you might see if 2x or 3x will get you where you need to be. I think it's a good tradeoff to use a smaller number of FETs to simplify the electrical design, then take that saved effort and put it into making the thermal side better to deal with the higher loss. 2x of those would definitely be capable of meeting your specs if the thermal solution is good enough.

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No I haven't looked into much detail yet, but 3x would be very good.

rhitee05 said:

Personally, my choice for the controller I hope to design someday is the IRFS3006-7. The SMT package and multiple source leads make it perfect for a really clean, low-inductance layout. SMT makes the thermal design more challenging, but I have a couple ideas that I think will take care of it. Probably not suitable for really big power, but should be ideal for a moderate setup.

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Looked it up... hummm, what a small beast! I'm not seeing exactly why should the thermal design be more challenging (I suppose the size is similar to a TO-220); because of a smaller tab?... It may be SMT but it can be soldered on the border of the PCB.

rhitee05 said:

I don't think I would need it for my planned design, but if I did want to go higher-power I would probably make the leap to water-cooling. That lets you deal with so much higher power density, so the FETs can be closer together and you can use fewer of them. I think you could easily design a 200A continuous controller using 2x paralleled 3006-7's with water cooling.

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Seems to me that it complicates things a little too much for gains. You may spare a inch or 2, but how about the volume and weight of all the stuff (some of it mechanical and therefore more prone to problems) you need to add for the water cooling circuit? (you're talking about e-bikes or e-motorcycles?)

No argument about designing with margin. Margin keeps the magic smoke where it's supposed to be! But you can have too much margin, and eventually you'll need to figure out what the sweet spot is. The cost of extra FETs isn't so much the price tag as the board space, layout difficulty, gate drive requirements, making sure current sharing is good, etc.

The challenge with the SMT FETs is just making sure there's a good thermal path since the heat wants to go into the board. Unless you do something really exotic like put all the FETs on the edge (not an ideal layout for electrical reasons), you have to pull the heat through the board. That's doable, it just means copper planes, lots of vias, and a careful thermal budget since that adds some thermal resistance. You can buy top-side mounted heatsinks which solder to a copper plane on both sides of the tab, but that's still not ideal. But the package current limit is even higher than the TO-247, slightly better thermals than TO-220, and the short leads make a really, really tight circuit layout possible. I assume the package must also allow a pretty big die since the Rdson is pretty similar to the TO-247 4368. I think it's a good combination of tradeoffs.

Another thing to keep in mind with having higher margin is that it may in fact reduce space: less heat -> smaller heatsink. Dissipated power is proportional to the current's square...

Just because it's SMT doesn't mean you really need to solder the tab to the PCB, right? In fact, I've even done the other way around, a few circuits mounting TH components SMT-like (like these ones). Another thing that sometimes leaves me wondering is that controller heatsinks (the box) seem to have a small air contact surface, and many isolate the switching devices right on the package with those "rubber pads", instead of connecting them 1st to a smaller heatsink and then isolating that heatsink from the box - maybe is more cost effective that way or the thermal resistance of the rubber pads is better than I think,
Lots and lots of vias... they are so thin (many vias also have a PCB manufacture cost impact).
What are the difficulties with electrical layout in a PCB's edge mounted device?

rhitee05 said:

package current limit is even higher than the TO-247,

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That's a good thing, because those values are measured with the device already "burning hot".

You could mount them over the PCB edge, but doing that in a good and reliable way would be difficult I think. You would have to make sure the mounting didn't stress the legs, spring clips would be required, and you'd need to use bus bars since the tab is the (only) drain connection. You'd also be more or less forced into a linear array configuration which is non-ideal. If you're going to do all that, you might as well just use a TO-247 package and mount the leads in an SMT-like way if you want. Doing so would increase the current rating of the package somewhat, since the legs could conduct heat into the board.

Vias do have cost impact on PCBs, but I'm not talking about hundreds and hundreds of micro-vias. For thermals, it would be better to use a smaller number of mid-large size vias. The hole-to-hole spacing will be set by the manufacturer's rules, so by using larger vias you increase the fraction of cross-sectional area they cover. Something like a grid of 30-mil vias on 50-mil center-to-center spacing, for example. Most of the low-volume hobby manufacturers don't charge by the via unless you have a really absurd number of them, so even if it's not a practical solution for mass-market it's fine for our purposes.

Njay said:

Another thing that sometimes leaves me wondering is that controller heatsinks (the box) seem to have a small air contact surface, and many isolate the switching devices right on the package with those "rubber pads", instead of connecting them 1st to a smaller heatsink and then isolating that heatsink from the box - maybe is more cost effective that way or the thermal resistance of the rubber pads is better than I think,

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That's cost-effective but terrible thermally. Those pads are not very good conductors of heat. You can get a lot better performance if you have a heatspreader first and then the isolation pad over a much larger area.

The thing I don't like in the idea of having the power switches dissipate heat through the PCB is that they'll be heating the rest of the components also. In an SMT-like board, I imagine a heatsink (your "heat spreader" actually) which is also bolted to the PCB for mechanical stiffness. Of course, that's a "custom" heat spreader, which may or not be difficult to get depending on the exact desired shape.

As for using springs, I think it is a must (when tabs are not soldered); actually, either springs or bolted bars. I've seen even cheap "chinese" controllers and DC-DC converters using small bolted iron bars to attach the power devices into the heatsink (through the famous rubber pad). It seems to me that this method not only avoids package warping but also allows better contact because the package can be pressed harder against the heatsink. I guess this also doesn't stress the legs too much.

Heating the entire board is a disadvantage of the SMT approach. You can keep it under control by allowing more isolation around the FETs for a thermal break and providing airflow to cool the rest of the board. I would plan on forced-air cooling anyhow, I think. Even so, the rest of the board will definitely be hotter than it would otherwise be. Fortunately, I don't think that's too much of an issue. Most components won't mind, and for the few that would (electrolytic caps, for example) can either get more airflow or just use higher-temp devices. Like anything else, its a design choice with advantages and disadvantages. Frankly, part of the reason I want to try it is because it's an unconventional approach. It could prove to be a great idea, or an example of why no one else does it that way!

rhitee05 said:

Frankly, part of the reason I want to try it is because it's an unconventional approach. It could prove to be a great idea, or an example of why no one else does it that way!

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That's pretty much enough reason for me! Go for it !

One of these days...

Njay, how is this coming along? still working on it? or have you moved on to something grander?

Still working on it, when time allows. There's still a lot to learn from this controller!