Circuit analysis of a cheap BMS, and why you shouldn't use one
- Thread starter MAXIMUM_AMPS
- Start date
MAXIMUM_AMPS
10 mW
- Joined
- Nov 13, 2019
- Messages
- 33
john61ct said:
Sorry, forgot a word, I meant come close as in IR. Voltage drop of a protected 18650 for example will always be higher than a similar unprotected cell due to added resistance of the protection FETs and shunt resistor.
I wouldn't recommend series modular batteries, as older cells in the string will have greater IR and lower capacity both of which lead to a difficult job for the balancing circuitry. As well as a load/charger that has to adapt to the varying voltage. Parallel modular is a solid option though, very common in DIY powerwalls.
DogDipstick
100 kW
So you are saying THESE are good? Thankyou.
Similar to what EM3EV uses in their batteries:
https://www.lithiumbatterypcb.com/produ ... tooth-bms/
Best thread i've read in a while.
Similar to what EM3EV uses in their batteries:
https://www.lithiumbatterypcb.com/produ ... tooth-bms/
Best thread i've read in a while.
Well in my case going to serial modules is a foundational design goal, important enough to "design around", overcome whatever the issues may be.
Isn't it the case that the only purpose of a shunt is to measure current?
I use separate BMs for coulomb counting and guesstimating pack SoC.
I think I'd prefer just using fuses, or fusible links as Tesla does, for OCP / short protection.
Therefore, shunt not needed in "the BMS"?
Also, are FETs essential to BMS functionality? As opposed to "how most BMS work". . .
Even if all the isolating/combining is done via old-school external contactors (solenoids / relays), current not flowing through the measurement / logic parts of the system?
On a different track, as I said propulsion usage with high C-rates is an edge case, usually plenty of Ah available so resistance not nearly as important for me than it would be for others.
As far as uneven wear goes, ongoing testing and rotation of modules, including retiring from rotation could handle that.
And as stated, balancing won't be done using resistance bleeding at sub-1A rates, whole concept seems flawed to me.
Isn't it the case that the only purpose of a shunt is to measure current?
I use separate BMs for coulomb counting and guesstimating pack SoC.
I think I'd prefer just using fuses, or fusible links as Tesla does, for OCP / short protection.
Therefore, shunt not needed in "the BMS"?
Also, are FETs essential to BMS functionality? As opposed to "how most BMS work". . .
Even if all the isolating/combining is done via old-school external contactors (solenoids / relays), current not flowing through the measurement / logic parts of the system?
On a different track, as I said propulsion usage with high C-rates is an edge case, usually plenty of Ah available so resistance not nearly as important for me than it would be for others.
As far as uneven wear goes, ongoing testing and rotation of modules, including retiring from rotation could handle that.
And as stated, balancing won't be done using resistance bleeding at sub-1A rates, whole concept seems flawed to me.
john61ct said:
MAXIMUM_AMPS
10 mW
- Joined
- Nov 13, 2019
- Messages
- 33
Interesting, why use series modules though? Is the load a passive component like a brushed DC motor? A SMPS with a wide range of input voltage?
In 1S protection circuits there's often (not always) a shunt on each cell, and with coulomb counting multi-cell systems the large shunt at the bottom of the pack is also used to measure coulombs.
Fusible links are definitely nice to have, and with something like a 20P battery, I'd consider them mandatory.
A resistance shunt is not critically necessary, larger systems use hall-effect current sensors to measure coulombs and instantaneous amps.
It really depends on the BMS chip used, most have dual gate drivers for CHG/DIS FETs, while others like the like BQ75614 for example will feature a built-in FET and snubber circuit for driving a contactor. Although it's not clear if the BQ75614 is made for a latching contactor or a non-latching type.
For a series modular system that could potentially have uneven capacities, it'd be very wise to use an LTC-3300-2 based solution, so you can get significantly more capacity out of the battery using active balancing.
For example say you have a stack of identical cells, just different levels of wear. Let's say older ones will have 20% less capacity than new. With charger-side balancing, the newer ones will be limited to 80% of their full capacity to the old ones acting as a bottleneck.
With active balancing, the BMS will distribute charge from the new ones to the older ones using a clever trick. The LTC-3300 pulses a FET in series with a transformer winding across the cell like shown:
This generates an isolated AC voltage on the other end of the transformer. Then, another LTC-3300 monitoring the lower charged cells can use its corresponding FETs as synchronous rectifiers to recover power from that AC voltage to charge the lower cells. Linear says 10A balancing current, but in theory with large enough cells and external components, you could balance at any speed you wanted to.
I will add that, the LTC-3300 solution and the support circuitry gets very expensive. Unless absolutely necessary, I'd recommend parallel expansion instead of series.
In 1S protection circuits there's often (not always) a shunt on each cell, and with coulomb counting multi-cell systems the large shunt at the bottom of the pack is also used to measure coulombs.
Fusible links are definitely nice to have, and with something like a 20P battery, I'd consider them mandatory.
A resistance shunt is not critically necessary, larger systems use hall-effect current sensors to measure coulombs and instantaneous amps.
It really depends on the BMS chip used, most have dual gate drivers for CHG/DIS FETs, while others like the like BQ75614 for example will feature a built-in FET and snubber circuit for driving a contactor. Although it's not clear if the BQ75614 is made for a latching contactor or a non-latching type.
For a series modular system that could potentially have uneven capacities, it'd be very wise to use an LTC-3300-2 based solution, so you can get significantly more capacity out of the battery using active balancing.
For example say you have a stack of identical cells, just different levels of wear. Let's say older ones will have 20% less capacity than new. With charger-side balancing, the newer ones will be limited to 80% of their full capacity to the old ones acting as a bottleneck.
With active balancing, the BMS will distribute charge from the new ones to the older ones using a clever trick. The LTC-3300 pulses a FET in series with a transformer winding across the cell like shown:
This generates an isolated AC voltage on the other end of the transformer. Then, another LTC-3300 monitoring the lower charged cells can use its corresponding FETs as synchronous rectifiers to recover power from that AC voltage to charge the lower cells. Linear says 10A balancing current, but in theory with large enough cells and external components, you could balance at any speed you wanted to.
I will add that, the LTC-3300 solution and the support circuitry gets very expensive. Unless absolutely necessary, I'd recommend parallel expansion instead of series.
Hi there,
I'm an engineer working at Analog Devices with a RF circuit design background and I have done some 10 watt class power electronics for various projects I've been in. I'm certainly not an expert in BMS systems, and I want to commend you for looking at this schematic and interpreting it mostly correctly as it isn't easy to do.
However, I think there are some fine technical details of the analysis that I disagree with you on, which may or may not change the safety conclusions but are important to get right:
The PNPs are active low, as you have noted, and the DW-01's output is high when there is a nominally working condition with no OVP or UVP. I fully agree with this. However, this means that VBE of the PNP is 0 in this condition, which means the PNP is in a non-conducting state when there is no OVP or UVP. This means the PNP is off when things are working normally. Each of the PNPs are connected via a 1M resistor to the base of the NPN, and the NPN transistor's collector is connected to the gate of the power NFET. If any PNP pushes current into the NPN's base, then the NPNs conduct. When the NPN conducts, then the gate of the NFET is brought to low voltage and the FET no longer conducts, thereby cutting the battery from the pack terminals.
The bottom power FETs turn on by default because B3 is connected to its each power fet gate through a 1M pull up resistor, which defaults the FETs to an on-unless-turned-off design.
So to put it more accurately, the PNPs normally block the current and when a OVP/UVP event happens the PNPs allow the current to flow, and the current flowing is what turns off the NFET transistor.
I don't have a good sense that when there is an esd event or failure on the DW-01 what actually happens at the OCP/ODP pins. Any appreciable current flowing into the OCP/ODP pin will cause the PNP to turn on and the battery pack to be disconnected though and this is the desired failsafe. I would think that a pull down resistor in addition to the 510K in series would guarantee this failsafe more reliably, though I'm not 100% sure if there aren't other negative effects associated with doing this.
Not sure if this changes any of the conclusions you drew though, as I think your broader point might still be valid.
I'm an engineer working at Analog Devices with a RF circuit design background and I have done some 10 watt class power electronics for various projects I've been in. I'm certainly not an expert in BMS systems, and I want to commend you for looking at this schematic and interpreting it mostly correctly as it isn't easy to do.
However, I think there are some fine technical details of the analysis that I disagree with you on, which may or may not change the safety conclusions but are important to get right:
The PNPs are active low, as you have noted, and the DW-01's output is high when there is a nominally working condition with no OVP or UVP. I fully agree with this. However, this means that VBE of the PNP is 0 in this condition, which means the PNP is in a non-conducting state when there is no OVP or UVP. This means the PNP is off when things are working normally. Each of the PNPs are connected via a 1M resistor to the base of the NPN, and the NPN transistor's collector is connected to the gate of the power NFET. If any PNP pushes current into the NPN's base, then the NPNs conduct. When the NPN conducts, then the gate of the NFET is brought to low voltage and the FET no longer conducts, thereby cutting the battery from the pack terminals.
The bottom power FETs turn on by default because B3 is connected to its each power fet gate through a 1M pull up resistor, which defaults the FETs to an on-unless-turned-off design.
So to put it more accurately, the PNPs normally block the current and when a OVP/UVP event happens the PNPs allow the current to flow, and the current flowing is what turns off the NFET transistor.
I don't have a good sense that when there is an esd event or failure on the DW-01 what actually happens at the OCP/ODP pins. Any appreciable current flowing into the OCP/ODP pin will cause the PNP to turn on and the battery pack to be disconnected though and this is the desired failsafe. I would think that a pull down resistor in addition to the 510K in series would guarantee this failsafe more reliably, though I'm not 100% sure if there aren't other negative effects associated with doing this.
Not sure if this changes any of the conclusions you drew though, as I think your broader point might still be valid.
MAXIMUM_AMPS said:
Similar threads
