How do i Miller Plateau Match mosfets?

[steveo]

Hey Everyone!

a definition i found on some thread.. i quote..

When you look at the datasheet for a MOSFET, in the gate charge characteristic you will see a flat, horizontal portion. That is the so-called Miller plateau. When the device switches, the gate voltage is actually clamped to the plateau voltage and stays there until sufficient charge has been added/ removed for the device to switch.
It is useful in estimating the driving requirements, because it tells you the voltage of the plateau and the required charge to switch the device. Thus, you can calculate the actual gate drive resistor, for a given switching time.


I'm gonna need to build up a couple of controllers for my 2wd x5 bmx bike & 2nd kmx build and i would like to Miller Plateau match the mosfets..

I've never done this before, so its a learning experience for me ...

after lots a talk with zombiess here on the es.. I understand that it is crutal to have the fets matched to avoid the black smoke let out..

For example...

say steveo is riding his x6 trike.. and i decide lets do a burnout. WOOOTTT.... during those miliseconds.. it is crutal that all the mosfets turn on and of at the exact same time or as close as possible...... so if one fet turns on at 3.5v.. and the other 3 in a bank turn on at 3.9v... for those miliseconds.. one fet would be taking all of the WOT amps!!!

From what i understand .. the mosfets must be matched on each bank... so for a 24 mosfet controller... you would need 6 sets of 4 fets each matched as close as possible for each bank...

so far i know i need a multimeter.... got my good old fluke.... and a Power Supply.. not sure what voltage to use.. and i also know the tempature must be same as possible for all fets tested or readings will be off...

so... how do i test each mosfet?

-steveo

 

[bobc]

The miller effect is capacitive feedback from the drain to the gate. The miller plateau is there during the time the drain voltage is (typically) falling (it's also there when switching off but you don't see those pictures so often). The lower your gate drive resistance, the shorter the plateau lasts & the higher your dV/dt on the drain. To understand a big trannie switching you have to think through each stage of the process - when the gate reaches the threshold voltage (something else to worry about matching?) it controls the current in the device (I is pretty much a quadratic function of Vgs - Vth). It's only when this current exceeds the load current that voltage movement happens & the voltage movement controls the whole miller business.
I suspect mismatch during switching is more attributable to layout & parasitic inductance than MOSFET gate behaviour matching; if you can get a good tight layout then paralleling should be fairly straightforward.
Looking at yr post, it sounds like you're trying to match phases rather than hard parallel devices. You are entering an unforgiving world with a potentially expensive learning experience - what advice can I give - dead time must be sufficient between top & bottom transistors on a leg. NOTE - if the dV/dt is sufficient to pull the gate around on (say) the bottom transistor of a leg (and if you see a miller plateau - you are in the zone), then it IS sufficient to pull it around on its opposite number (which sees exactly the same dV/dt) So you HAVE to pull off harder than on, or you get a blip of shoot- through current every time you switch. The low threshold voltage of most power MOSFETs is not helping here. Also remember that the reverse transfer capacitance (miller capacitance) is voltage dependent, gets MUCH higher at low Vds.
Good luck!
Bob

 

[steveo]

The miller effect is capacitive feedback from the drain to the gate. The miller plateau is there during the time the drain voltage is (typically) falling (it's also there when switching off but you don't see those pictures so often). The lower your gate drive resistance, the shorter the plateau lasts & the higher your dV/dt on the drain. To understand a big trannie switching you have to think through each stage of the process - when the gate reaches the threshold voltage (something else to worry about matching?) it controls the current in the device (I is pretty much a quadratic function of Vgs - Vth). It's only when this current exceeds the load current that voltage movement happens & the voltage movement controls the whole miller business.
I suspect mismatch during switching is more attributable to layout & parasitic inductance than MOSFET gate behaviour matching; if you can get a good tight layout then paralleling should be fairly straightforward.
Looking at yr post, it sounds like you're trying to match phases rather than hard parallel devices. You are entering an unforgiving world with a potentially expensive learning experience - what advice can I give - dead time must be sufficient between top & bottom transistors on a leg. NOTE - if the dV/dt is sufficient to pull the gate around on (say) the bottom transistor of a leg (and if you see a miller plateau - you are in the zone), then it IS sufficient to pull it around on its opposite number (which sees exactly the same dV/dt) So you HAVE to pull off harder than on, or you get a blip of shoot- through current every time you switch. The low threshold voltage of most power MOSFETs is not helping here. Also remember that the reverse transfer capacitance (miller capacitance) is voltage dependent, gets MUCH higher at low Vds.
Good luck!
Bob

thanks for all your info...

so can i test the mosfet with some simple tools ?... this is sounding more complicated then i thought...

thanks
-steveo

 

[adrian_sm]

Hook up an oscilloscope and watch the gate voltage while you switch FETs.

But as bobc mentioned the board layout & component variation will also affect things. So perfectly matched fets on the bench, may behave differently once in your controller.

 

[steveo]

Hook up an oscilloscope and watch the gate voltage while you switch FETs.

But as bobc mentioned the board layout & component variation will also affect things. So perfectly matched fets on the bench, may behave differently once in your controller.

I do agree, the board layout / component variation would play a big roll... do i need to use a oscilloscope or can i use my fluke multimeter...?

would i toggle the voltage between say 3 - 5v to see when it turn on and off?..

thanks
-steveo

 

[adrian_sm]

Probably better to wait for an Elec Eng to answer but I'll fill in the time and hopefully not get too much wrong.

There are two things I think you would be interested in measured.
1) the Vgs(th) the Gate voltage threshold where switching starts to occur
2) Qg gate charge, or essentially how long the switch takes to full turn on.

Both these will vary FET to FET, and both will impact how long after the controller asks the FET to switch, it is actually finished switching.

You should be able to measure (1) with a multimeter by slowing increasing gate voltage, and measuring the resistance, but (2) really needs to see time scale of the switching event.

Here is the typical graph pulled from the IRFB4110 datasheet for reference.

 

[bigmoose]

Texaspyro exposed matching publicly first, I believe... so he should get the credit. Here is one of his posts on the subject:

http://endless-sphere.com/forums/viewtopic.php?p=370662#p370662

I have found that FETs from the same batch tend to have very well matched Rdson values, but their gate threshold voltages can still be quite different. For the 100 IRFP2907 FETs that I bought for some welders, the Rds value ranged from 0.2 to 200K ohms at the same gate drive voltage. At full on the Rds values were within around 10 micro ohms.

I always match my paralleled FETs for threshold voltage. I usually do this by driving the gate with a fixed voltage that is in the FETs linear region (say 3-4V on a 10 Vg FET) and matching the FETs for their Rds value. Not quite as good as putting them on a curve tracer, but I have found it works about as well.

http://endless-sphere.com/forums/viewtopic.php?p=280216#p280216

There are 18 IRFP2907 FETs in the power switch. Net ON resistance is around 0.17 milliohms. They do not get even slightly above room temp... no heatsinks or fans needed. I bought 100 FETs and matched them in 5 groups of 18 for gate threshold voltage. Matching for gate threshold voltage assures that all the paralled FETs turn on at the same time and minimizes stress on the FETs. All the FETs had identical full-on resistances of 3.100 +/- 0.100 milliohms, so not much to be gained by matching for full-on resistance.

You are matching them so they load share through the transient linear region (think switching region) as they go towards "saturation"

 

[zombiess]

I will post up a quick and dirty method tomorrow. All you need is a regulated variable supply.. one made from an lm317 and a 25 turn pot ( you need 25 turns to get the resolution required) and an ohm meter that you can lock the range on. If it switches it messes up the impedance. As an alternative you can use a dmm to read voltage as long as it reads x.XXX digits and a fixed resistor. You also need to work without ever touching the fet with your hands until its measured.

I have a data logger running on my new matcher I'm designing to see if I can come up with a temperature compensation formula / method for the transconductance zone. Sampling every 15 mins with the window open for 16 hours. If the formula fails then plan b is a pid loop controlling vgs to a reference fet .

 

[bobc]

"How do I match with simple tools" - for paralleling MOSFETs there's not a lot open to you. Zombiess idea ^^^^^^ sounds good for threshold matching but you'd also need to match rev. trans. capacitance and transconductance in the real world.... If I needed to do it I think I'd get me a fast scope & one of those PCB trace current probes - we got one at work & the bandwidth is excellent + it would show you actual device current under operating conditions. It wasn't silly money if I remember right. You just need to check drain current on every FET & ensure none is taking too much during the switching transient (adjust by altering that transistor's gate resistor...) Sounds like a lot of palaver - perhaps a bit of "headroom" would be more appropriate ;^)

 

[Arlo1]

Come on Zombies I have been waiting for you to post that info for months..... Pictures?

 

[steveo]

so... i need...

-a regulated a variable supply.. What votage range do i need?... could i use a 6v psu supply like a meanwell ? variable from say 3.3 - 6v with a 25 turn pot for example.... and it has to use a lm317 chip?... why is the lm317 chip so important?

-fluke multimeter... check

-don't touch the mosfet when testing

-a fixed resistor?.. what value and wattage?

thanks
-steveo

I will post up a quick and dirty method tomorrow. All you need is a regulated variable supply.. one made from an lm317 and a 25 turn pot ( you need 25 turns to get the resolution required) and an ohm meter that you can lock the range on. If it switches it messes up the impedance. As an alternative you can use a dmm to read voltage as long as it reads x.XXX digits and a fixed resistor. You also need to work without ever touching the fet with your hands until its measured.

I have a data logger running on my new matcher I'm designing to see if I can come up with a temperature compensation formula / method for the transconductance zone. Sampling every 15 mins with the window open for 16 hours. If the formula fails then plan b is a pid loop controlling vgs to a reference fet .

 

[Arlo1]

so... i need...

-a regulated a variable supply.. What votage range do i need?... could i use a 6v psu supply like a meanwell ? variable from say 3.3 - 6v with a 25 turn pot for example.... and it has to use a lm317 chip?... why is the lm317 chip so important?

-fluke multimeter... check

-don't touch the mosfet when testing

-a fixed resistor?.. what value and wattage?

thanks
-steveo

I will post up a quick and dirty method tomorrow. All you need is a regulated variable supply.. one made from an lm317 and a 25 turn pot ( you need 25 turns to get the resolution required) and an ohm meter that you can lock the range on. If it switches it messes up the impedance. As an alternative you can use a dmm to read voltage as long as it reads x.XXX digits and a fixed resistor. You also need to work without ever touching the fet with your hands until its measured.

I have a data logger running on my new matcher I'm designing to see if I can come up with a temperature compensation formula / method for the transconductance zone. Sampling every 15 mins with the window open for 16 hours. If the formula fails then plan b is a pid loop controlling vgs to a reference fet .

Steveo there is lots of ways to get the voltage you need
1 lm317 is an adjustable regulator
You want to look at the charts for the fets you.are testing and set the voltage to the gate to be in the middle of the miller plateau voltage. This is where a 25 turn pot on the adjustment pin of the lm 317 will make life easy. But make sure you have a perfactly stable voltage this is another reason the lm317 would work well.

 

[zombiess]

This is a very crude way to match, but it will prevent you from paralleling drastically miss matched FETs together which can cause un equal current sharing and subsequently blown FETs at higher current levels.

There are a few ways to do this but there are a few critical things that must be done during the process to keep the matching close.

1. Only handle the FET’s with pliers or tools, never touch them with something that is not room temperature.

2. Make sure the FETs are in the room for at least 30 mins so that they stabilize in temperature.

3. You need a stable voltage supply capable of being varied from 0-5V in 0.001v increments. It is critical that the supply is stable to within +/- 0.002V if you want a close match.

4. You need a high impedance multimeter that can be locked into a range. It need to be locked into a range because auto ranging will often change the impedance of the meter and effect the readings.

The power supply can be built from an LM317 voltage regulator using a 25turn pot for adjustment, pick values that allow you to have a range of 2-5V as this is all you will typically need. As an alternative you can use a 5V LM7805/LM7812 and a 25 turn put setup as a voltage divider fed into an NPN emitter follower buffer to supply the gate voltage. This is how I do it with a micro controller using digital pots to set my gate voltage.

If you are going to use an ohm meter you want to have a decent range from 0-50kohm or 0-100kohm and lock it to this range, no auto ranging allowed.

Hook up your N-MOSFET to the ohmmeter to the FET drain pin and the other lead to the source pin. Variable power supply +V goes to the gate, ground to the source. Start varying the voltage until you get a reading on the meter. For an IRFB4115 you will find that you will be in the 0-100kohm range around 3.900-4.000 Vgs.

Write down the ohm reading and create separate piles of FETs, grouping them every 10kohm initially is a good start. If one reads off the scale too high, place it in a separate pile, lower than 5k place it in a separate pile. You will need to go back and measure these FET piles at a different VGS. To bring the resistance down increase Vgs, to raise it, lower Vgs. The response is linear as long as you stay in the transconductance zone of the FET. Inevitably you will start to see a trend emerging of where you have more FETs in one or two piles vs the others.

Things that will mess up you readings. Temperature change in the room of more the 0.5C, handling the FET with your hands for even a fraction of a second, your power supply drifting more than a few millivolts. While this makes the matching process harder, you will at least be able to weed out piles of FETs that are similar in characteristics. This alone should get you into a +/- 10% match range even with all the problems it presents. Remember the goal is to weed out the FETs which are drastically different from each other so that you can parallel similar FETs and increase your chances of having them survive as a group.

Once you have your piles it should be clear that if you parallel an FET that measures 200k ohms at 4.000 Vgs with one that measures 7k ohms Vgs you are going to have problem with current sharing while they are transferring through the transconductance zone.

If you want to use a volt meter instead of an ohmmeter to measure. Use a 10kohm resistor connected to +5v and the other end to the drain. Ground the source pin. Hook your variable power supply to the gate and to the ground. Your meter ground goes to the ground and the positive goes to the junction of the drain pin and the 10k ohm resistor. Now vary your gate voltage and you will see the voltage changing on your meter.

To calculate the ohms of the FET drain to source connection use the following formula
Ohms = 10000 / (5V/ measured voltage -1)
You can test this by substituting another resistor for the FET and making the measurement then running it through the equation. It should give you the value of the resistor in ohms.

Example. Putting a 10k resistor in place of the FET we now have a voltage divider with two 10kohm resistors and a 5v supply. Our measured voltage should be ~ 2.500 volts.
5V / 2.5v measured = 2.000v
2.000v – 1 = 1.000V
10000 ohms / 1.000V = 10,000 ohms resistor that we are measuring. This is how use measure resistance with a micro controller using an ADC.

Sorry that this sounds more complex than it really is. I am building a few FET matchers that take a lot of the human error and work out of the process. Current version can measure 7 FETs at a time and automatically spits out a group number for them so matching can be done quickly.

If you have dual setups to do this it can get you closer matches. Use 2 meters, setup one meter and 1 fet as a reference. As this FET measurement drifts due to temperature or changes in Vgs you can compensate by adjust the gate voltage to bring it back to it's original reading.

If you match FETs on different days or even several hours apart, it is best to setup one FET you previously measured and adjust the gate voltage to it until you get it's reading back to the reading you initially measured it at. Now you can more closely group to your original batch.

For even closer grouping, go back into your individual piles and sort through them again and group by smaller values and then place them all in order from lowest to highest so that when you want to create a parallel group all you have to do is grab the next group in series from the pile and you know they are matched closely.

 

[zombiess]

No comments?

I guess now you see why I use a micro controller to speed up the process dramatically. My first version did 4 FETs at a time and only took me about 4 hours to bread board and code, made a few minor tweaks later. I would sort out into big groups, then those into smaller groups, then before building the bars I did one last match to find the most closely matching FETs. The last stage is the most important because you want FETs that all display values very close to each other. The actual Vgs you test at doesn't matter much as long as it's in range of my matcher. I try not to go over 99k ohms because I get easier to read numbers from them jumping around less. Temperature compensation doesn't matter either at this point as you just want your parallel group to have ohm readings that are within 10% or better of each other.

I realize this isn't the most elegant method of matching, but it's infinitely better than just random selection.

Wife and I will be sorting around 750 IRFB4115 FETs tomorrow... fun...

 

[Arlo1]

No comments?


Wife and I will be sorting around 750 IRFB4115 FETs tomorrow... fun...

Get a video so we understand it better.


I thought you only needed to feed a voltage to the gate and measure the resistance at the same time?

 

[zombiess]

OK, I just dug through my spread sheet and gathered up my logs from yesterday and today and came up with what I think might be a temperature correction factor. It's 3rd order polynomial and works in the transconductance zone on a single FET I am using as my calibration FET.

The FETs have a negative temperature coefficient so I came up with an inverse percentage from my data to compensate for temp drift. It's far from perfect, but if it works across multiple FETs or even a single type of FET (IFRB4115 FETs) in my case it will be good enough for my use which is what I really care about.

y= a 0.10 to 4.00 multiplier with 1.00 (parity) at 24.8C. I aimed for 25c, but it is what it is, I'll just correct it on the software and add 0.2c to my temp readings as the actual reading doesn't matter that much.

y = 0.0003677422x3 - 0.0157576557x2 + 0.2328295304x - 0.6886150315

I have only tested my single IRFB4115 FET, but I varied the temperature range from 15c to 35c and the ohm value only drifted a little bit, good enough for my application. I also varied the gate voltage from 3.800 to 3.950 and it worked across this Vgs range. I mucked up the test a little with the icecube though. Things got a little out of whack due to some mysterious water in the breadboard... dunno how that got in there :lol:

I'll be hooking up multiple random FETs tomorrow and watch how they change over a small temperature range that naturally varies in my office. If all works as I hope, the calibration FET will keep the other FETs readings mostly temperature stable so I don't have to worry as much about matching under different circumstances. This is nice because it will allow me to set a Vgs and not worry about compensating for the temperature drift. I'm crossing my fingers. If it doesn't work then I'm just going to adjust the Vgs on the fly to all FETs under test based off a saved value for the calibration FET. This is easier, but I wanted to see if I had the skills to pull off something a little more complicated.

 

[Arlo1]

I just did a youtube video while I was matching up all my irfp4568 fets tonight.
:Edit As zombies pointed out If you have a normal board this will not work the same way I show it in the video. My boards are special. I built them this way so I could get the fets closer to the caps but the low side drain in this setup is not parallel until I insert the Aluminum with graphite paper on it to the backs of the low side fets. They will be conducting though the aluminum heat sink to the phase wire.
[youtube]mYcjsMmaWzc[/youtube]

 

[zombiess]

See my post in your other thread, it looks like you are doing it wrong. Need to do them one at a time, not when they are paralleled.

 

[Arlo1]

See my post in your other thread, it looks like you are doing it wrong. Need to do them one at a time, not when they are paralleled.

As I mentioned in the other thread they are not paralleled. The Source is common but the drain from the low side fets is not paralleled until I insert the aluminum T in the bottom with the graphite paper on it. Sorry I did not mention this in the video.

 

[zombiess]

See my post in your other thread, it looks like you are doing it wrong. Need to do them one at a time, not when they are paralleled.

As I mentioned in the other thread they are not paralleled. The Source is common but the drain from the low side fets is not paralleled until I insert the aluminum T in the bottom with the graphite paper on it. Sorry I did not mention this in the video.

Good to hear. I was trying to check your PCB from the video before I posted, but I figured better play it safe. I'm more concerned about others who would try after watching your video and have them in parallel without realizing it.

 

[steveo]

Here is my video

I did this a few weeks ago.. I think i did it wrong

[youtube]3rP3lMk2nCc[/youtube]

Im tryin..

-Steveo

 

[Arlo1]

I saw your video Steveo And I don't think its really wrong. You were just finding the transition point to full on and writing down the voltage. Realy its the same thing.
But I think just using a constant voltage and measuring resistance might be easier/quicker and more acuate. The biggest think I found as zombies pointed out is temperature will cause them to change a lot. So I put them all in by holding onto the plastic edge then let them stabilize for a bit then I would take a reading and wright it down and then double check it didn't change. If you have a batch of fets you should do them all at once so ambient temp stays the same. I found I could even blow on them to make a change in resistance.

BTW the lm317 is a bastard their is the calculator and then there is the pinout schematic they don't show the legs in the same spot. I have made this mistake many times maybe that's your problem?

 

[zombiess]

I will create a how to video that simplifies things a bit. Should help out with any confusion for those who want to try this.

 

[Arlo1]

I will create a how to video that simplifies things a bit. Should help out with any confusion for those who want to try this.

I thought that's what I did?

A couple posts ago you tried to type a simple post how to do it and went way into detail lol.

Its this simple turn fet on part way then mesure resistance. That's it!
Make sure the temp and the voltage to the gate is the same on all fets tested.
Put fets into closest groups and you are done!