Alan, our designs seem to converge at an alarming rate! LOL.
Planning on using as much balancing current as I can. Clearly some thermal management will be needed. The chip has a thermal pad, so hopefully that can be used to good effect. This is one of the things I want to test in an actual setup to verify the thermal model. Thermal modeling is one of the things I do in my day job. Worst case would be to use external FETs and larger resistors, which my current design uses anyway. It would be nice to have to, though, for cost reasons.
If you balance a pack during every charge, only minimal balancing is required anyway, assuming you have a good pack. The balancing history quickly identifies a duff cell and is flagged to the user.