BMS, how I designed mine. A semi intelligent dummies guide.

[maxwell]

I have had lots of interest in my BMS, so here goes attempting to show how and why I did it.

What a lithium BMS system should do...

1. Prevent overcharge

2. Prevent overdischarge

3. Prevent overcurrent

4. Balance the cells during charging.

5. Charge the battery, it is part of the management after all.

The first three are done by monitoring the parameter concerned and disconnecting the battery on excursion beyond the limit decided upon.

Balancing is done by comparing the individual parallel block of cells with a reference and dumpung an amount of the charging current to equalise the voltages.

Lets decide on some figures, look up on data sheets is a more plausible senario. These are for my dual 4p14s pack.

1. Charging voltage 4.1V, this will give about 90% capacity and a much longer life. Charge current 2A, (for a sensibly sized charger) giving about 1/2C per cell and charge current cut off of 200mA, 50mA/cell, around 5% of C.

2. Low voltage trip point, 2.7V, this will be measured under load too so it is not too low.

3. Overcurrent set point of 25A, thats 2.9C, my cells are rated at 1.5C continuous the controller should limit the current and I don't want any false trips.

As I was designing a charger I have put all the charging limits in this, the balancing is in the pack, saves a load of connexions to the charger (26 less).

Thats the outline, next the low voltage trip.

 

[maxwell]

The main part is the TLV3012 reference/comparator chip Q1, the cell voltage is compared to the in chip reference of 1.242V using R3 and R4 to drop cell voltage to 1.242V (it's a little lower because of the hysteresis circuit, good enough for explanation), I said earlier it was 2.7V, in reality nearer 2.78V, engineering is about being good enough, perfection costs an infinite amount of money.

Q1 has R10 and R17 round it to give some hysteresis (go Google) giving a clean output pulse.

When the voltage at the juction of R3 and R4 drops below 1.242 (less a bit because of the hysteresis 1.129V) the output of Q1 will go high turning on the FET Q3. The drain of which is connected, via R1 to limit the current and D1 to stop reverse currents, to the other low voltage trips on all the cells in parallel. So when any LV trip board trips a signal is sent to the breaker opening it.

Breaker section next.

 

[maxwell]

When the previous circuit pulls X5 low Q1 is turned on, this then turns on Q3 sending a current through the trip coil of the breaker (connected to terminals 'coil') tripping it, D4 preventing the back emf of the coil damaging anything.

D2, R2, R4, R10, R11 & D3 limit current and protect the gates from overvoltage.

There is a large (1000uF) capacitor across X7 and X9 to keep the volts up during a short circuit, more of which later.

 

[fitek]

Nice posts, Maxwell. Good to see its all thought out and you've got schematics. I know I will have to get around to a BMS once I work out the motor for my bike and everything. I'll bookmark this page Look forward to seeing more if you're going to post it.

 

[maxwell]

More soon, bit busy...

 

[maxwell]

... and had a design failure (it happens), oops, redesign on the way hang on.