I think it should be pretty straightforward to do using discrete mosfets. It can be made to run slow enough such that generic (cheap) optoisolators will suffice for the gate drive. Then you have N-1 capacitors for N cells switched back and forth (alternating offset of 0 and 1) by 2N mosfets. The control circuit should run two mosfet groups with a dead time interval to avoid quiescent current. Caps should probably be of MLCC type for longivety. Mosfets for this switching network are low voltage (cheap).
The benefit of such balancer is that it can be run continuously or periodically during discharge as well. If it has enough power then per cell LVC becomes unnecessary. Moreover the battery capacity can even be slightly extended - the pack capacity is no more limited by the weakest cell.
The benefit of such balancer is that it can be run continuously or periodically during discharge as well. If it has enough power then per cell LVC becomes unnecessary. Moreover the battery capacity can even be slightly extended - the pack capacity is no more limited by the weakest cell.