That last post confused me.
2 comparators, could be on the same shunt, bit more complicated with 2 shunts instead of 3.
<edit>3 shunts? One, optimized for speed, for HW shutdown, the other two optimized for accuracy, for phase current.<endedit>
One comparator would drive the enable pins on the drivers, to off.
The other would be connected to the fault input on the PIC, and would be set to a lower current than the first.
Normally the first wouldn't trip because the fault input would take care of it, and the program would probably temporarily reduce the pulse width so it didn't happen again?
If the first trips, it would probably indicate a 'fault' of some sort, and, if there's an appropriate input, the processor would act accordingly. The fault input keeps the PWM off for the rest of the cycle, so the program would have time without resorting to RC delays like I implied in the last post.
The big question is 'how fast is the enable pin based shutdown compared to the fault input on the processor'. I find no delay specs for the fault input on the dsPIC30F4012. OK, I did find it in the 3011 pdf, 50ns.
I think maybe I'm still confused.
Is redundant fault protection needed, or is the driver delay the problem, or just in case of processor or firmware faults.