Lebowski
10 MW
you will need snubbers !
Arlo's power stage Leaf controller runs and drives page 103
- Thread starter Arlo1
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If I find I need them I will put them acroos the traces on the bottom.bearing said:
Remember this is a double use board so my big plan is build one little wussy 18 fet controller then use the same design to run to my current powerstage. Which has the fets off the board. So the snubers (which I found I don't need because its a good layout) would go on the fets themselves. If I find I do need them which I am very VERY confident I wont I will edit boards in the next batch to add them. Remember this is a work in progress.
Lebowski
10 MW
Arlo1 said:
I'm not betting, you're betting the life of poor innocent FETs, lambs to the slaughter :|
Na as I found I with my tests already the ringing goes away as I raise the voltage, I will test it of course. and I will have to see how it works with the to220 package fets as well.
The design with the buffer fets is good for preventing ringing! Anyways here is what I think is a finished protoboard now to figure out who to send the Gerber's to to get them here in a timely/costly fashion.
The design with the buffer fets is good for preventing ringing! Anyways here is what I think is a finished protoboard now to figure out who to send the Gerber's to to get them here in a timely/costly fashion.
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Lebowski
10 MW
circuit said:Um, all gates in parallel?... This does not smell right to me[/qoute]
Agree, better to use multiple gate resistors
Not what I have been taught, its better to run 1 gate resistor so things are more even!Lebowski said:circuit said:Um, all gates in parallel?... This does not smell right to me
Agree, better to use multiple gate resistors
I do understand you can get slight differences in fets. But it is best to run from one gate resistor if you can. I will see how it goes. As well I will fet match per set of three as Jeremy and a couple others have.circuit said:
The second set of boards can have provisions for a second low value gate resistor to "tune" each fet sepratly on the BIG powerstage.
nieles
10 kW
I have to spend some time and tripple check now you have me worried..... But the drain from 1&2 go to each side of a resistor (r1) and the drain from 3 and 4 go to their respected resistor (r1). It's hard to see from the screen shot. But I put the drains of all buffer fets facing inwards.
It might make more sense zoomed in a bit. So here you go. Q1 and Q3 both connect to the 12v input from the caps and from the jumper as you can see with the green trace.
Now I just noticed the 2 bootstrap diodes are not joined on the out puts. I will edit that for the future and for now I can just run a jumper.
Now I just noticed the 2 bootstrap diodes are not joined on the out puts. I will edit that for the future and for now I can just run a jumper.
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nieles
10 kW
didn't want to worry you, just wanted to make sure it is connected the right way.
your schematic looks good
your schematic looks good
casainho
10 GW
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Hey Arlo1!! Nice job on KiCAD. I also designed a schematic recently for Smart EBike Controller and later I will need to work the PCB.
I just found that you also bought a Rigol oscilloscope, the same as me!! Seems we are using the same tools
I don't know if you can, but seems your schematic could me more readable if you use labels. See mine as example (prototype V2):
I just found that you also bought a Rigol oscilloscope, the same as me!! Seems we are using the same tools
I don't know if you can, but seems your schematic could me more readable if you use labels. See mine as example (prototype V2):
Circuit when you see what I am trying to run for a powerstage and how my plan to lay it out is you might understand why I laid it out this way.circuit said:
As for the auto router I can edit traces after or try to do it all by hand but it does try to make the traces short as it can and i can change some of the design rules before running the autorouter and make it do things differently. At this point the autorouter is likely far better then I am!
Ok so as I design a board dedicated 100% to the 48 fet board I face one problem.
The distance from the gates of the 8 fets will be about 6 inches apart so my only idea is to double up the second set of buffer fets on each side of the H bridge so they can have shorter loop inductance.
So as seenhere Figure 11 it would mean two sets of Q3 and Q4 This would mean there would be the gates from 4 fets powered buy one set of q3/q4 and the other 4 gates powered by the other set of q3/q4. Meaning the distance between gates will be ~3 inches of a group of 4.
The distance from the gates of the 8 fets will be about 6 inches apart so my only idea is to double up the second set of buffer fets on each side of the H bridge so they can have shorter loop inductance.
So as seenhere Figure 11 it would mean two sets of Q3 and Q4 This would mean there would be the gates from 4 fets powered buy one set of q3/q4 and the other 4 gates powered by the other set of q3/q4. Meaning the distance between gates will be ~3 inches of a group of 4.
Lebowski
10 MW
Are you using the new v1.1 i sent you ?
bigmoose
1 MW
Paralleling 8 FETs in discrete packages is a real challenge. It is not an area that I have direct experience with. I cringe at using two discrete driver paths to a common FET bank. Any mismatch in timing, and that on the order of 10 nS, will start to skew the current paths. Absolute matching of driver timing is mandatory.
What we have seen in that area is the custom packaging of the 6 to 8 large die in a package, as a brick or a puck. You may want to dissect how Sevcon drove their multiple TO220 FET banks, or think of subpackaging your 8 FETs into a brick for further integration. Something where the TO247/TO264 packages are closer together.
An 8 inch spread on the Source Bus makes is going to make for an interesting definition of "ground." If the 8 FETs have different source potentials, they will have individual, and therefore different gate drive characteristics. Individual FETs will then hit the miller plateau at different times...
What we have seen in that area is the custom packaging of the 6 to 8 large die in a package, as a brick or a puck. You may want to dissect how Sevcon drove their multiple TO220 FET banks, or think of subpackaging your 8 FETs into a brick for further integration. Something where the TO247/TO264 packages are closer together.
An 8 inch spread on the Source Bus makes is going to make for an interesting definition of "ground." If the 8 FETs have different source potentials, they will have individual, and therefore different gate drive characteristics. Individual FETs will then hit the miller plateau at different times...
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