rhitee05
10 kW
I'm obviously coming a little late to the party, but I designed a fast-trip circuit just like this for a previous controller idea. It uses a fast comparator as the input to an S-R latch which disables the driver. You could do this either through the EN pin on the driver chip (if available), or using an XOR gate on the PWM signal. The latch is reset by the falling edge of the PWM so the driver is guaranteed to be off for the rest of the cycle. That should give the uP time to intervene. Even if it doesn't, the latch will trip again during the next cycle so the FETs are still protected.
Getting a fast measurement is a problem. If you want response time <1 us, that means >1 MHz bandwidth. All of the Allegro hall sensors have bandwidths of 100 kHz or less. In my circuit I used the low-side FET itself as the shunt to measure current. It won't be very accurate, but if you have several FETs in parallel the variance will tend to average out somewhat. The biggest issue is the change in Rdson over temperature. You could design your circuit based on the resistance at a nominal operating temperature and consider it a "feature" that at higher temps, the higher resistance will cause the circuit to trip at lower current. Or, you could measure the FET temperature and adjust the set point accordingly.
There are a few other little details that I dealt with when I designed that circuit, like what happens when the lower FET is off. I'll see if I can dig it up.
Getting a fast measurement is a problem. If you want response time <1 us, that means >1 MHz bandwidth. All of the Allegro hall sensors have bandwidths of 100 kHz or less. In my circuit I used the low-side FET itself as the shunt to measure current. It won't be very accurate, but if you have several FETs in parallel the variance will tend to average out somewhat. The biggest issue is the change in Rdson over temperature. You could design your circuit based on the resistance at a nominal operating temperature and consider it a "feature" that at higher temps, the higher resistance will cause the circuit to trip at lower current. Or, you could measure the FET temperature and adjust the set point accordingly.
There are a few other little details that I dealt with when I designed that circuit, like what happens when the lower FET is off. I'll see if I can dig it up.