Arlo's power stage Leaf controller runs and drives page 103

[Arlo1]

I thought this would work with just the pull down connected to the gate.... http://ww1.microchip.com/downloads/en/DeviceDoc/22019B.pdf

SO I connect the hi gate to this the driver inverts the signal and shorts out the gate to source of the low side fets when the hi side is on. But when the hi side is off it does not try to drive the gate high because the fet driver has 2 outputs. 1 is to pull low and the other is to pull hi....

Edit no I don't think it will because I need something that doesn't turn the gate on only clamps it off. So either a source sink output or a driver that doesn't need voltage hooked to it.

 

[IanFiTheDwarf]

OK after I get this one working as best as I can with these fets then I'm onto the next build with the ixfk230n205 These have a bigger surface area to pull the heat out from. My design should pull the heat out extremely well with the graphite paper.
They are 160 amp package limited and a little higher rdson at 7.5 mohm. I designed these boards for use with either fet so people can choose.

I was having a look at them as well but am swaying towards the IXFK170N20T-ND. Its only 170A but if the package limit is 160A that shouldn’t make any difference, what will make a difference is the higher rds on of 10.5mohm but that’s not necessarily going to matter that much if the cooling is good enough. And the biggest point for me is they are a little over half the price of the ixfk230n205.

 

[HighHopes]

I am seeing up to ~5.8v on the low gate from miller

honestly, that makes me feel better. i was expecting this type of result due to heatsink being used to also pass current because heatsink is a big capacitor.

i'm not sure yet how you are going to control that microchip mosfet, but here are my thoughts anyway:
- the mosfet driver is 6A rated. that is WAY high. remember, the power mosfet is already off when the clamp is engaged so even 1A rated mosfet is more than enough. such a small mosfet does not require 6A driver. no problem to keep it, just extra cost.
- timing is very important for the clamp. after power mosfet is OFF it is imperative that the clamp is engaged immediately. generally it is difficult to acheive this timing when the clamp signal comes from external of the gate driver due to the delays it usually takes to bring the signal across the isolation barrier. now in your bootstrap case this might not be a problem because you don't really have an isolation so likely your signal propegation delay is not too much. post a schematic when you are ready to discuss.

by the way, if you took a ceramic X7R capacitor and attached as close as possible to power mosfet gate/source. lets say you did 10nF which is probably good size for your application, what would the increase power requirement be?:
P=C*fsw*delta_V^2
P=10nF*40,000Hz*15V^2
P=90mW

 

[Arlo1]

I don't see the need for a schematic but here you go...

I would love to find a small cheep driver or fet to use as a clamp. I think timing from the hi side will be perfect! And It will be adjustable from the dead time and gate resistors.
The one that has the Hi side signal can be an inverted fet driver (much easier to use) but I cant seem to find what I need for a fet driver with inverted and a separate sink and source pin Like the TD350

 

[Arlo1]

OK after searching 44pages of inverting fet drivers I will have to order the non inverting type from diodes.com and I will just invert the signal going to it. I can't find a single inverting fet driver that will not turn on the gate after clamping it. To be clear the goal is to just clamp the gate to source with a get driver from an inverted signal from the hi side.

 

[nieles]

I dont know of this will work, because you need a return path from the hi side driver to the source of the low side switch (gnd).

 

[Arlo1]

I dont know of this will work, because you need a return path from the hi side driver to the source of the low side switch (gnd).

Yes I will use the signal from the brain because its not delayed and has a logic from common ground.

 

[nieles]

Ah yes makes sense. But how will you do this for the high side FETs? The same problems apply for those FETs too right?

 

[Arlo1]

Ah yes makes sense. But how will you do this for the high side FETs? The same problems apply for those FETs too right?

I don't think the hi side FETs get the miller effect. We will have to ask high hopes that one. But if the do it will all be in reverse for the hi side with a hi side fet driver !

 

[HighHopes]

for true sine-pwm or space vector drive then it can happen on both upper or lower. for miller effect all you need is a large dV/dt in correct polarity. so every switch, upper or lower, you have a large dV/dt because the voltage goes from zero (mosfet ON) to bus voltage (mosfet OFF). so that's sure given. then, the polarity.. during phase output current positive half cycle, the lower mosfet experience miller effect and during negative half cycle the upper mosfet.

actually this makes sense from another view, in sine-pwm or space vector drives it is a symmetrical design & system so you should expect on both.

there is TD350 gate drive chip which has most features, then TD351 which has less for lower cost drive. a good app-note on TD351 explains some of the features that both driver chips have here: http://www.bdtic.com/DownLoad/ST/AN2123.pdf

 

[Arlo1]

Ok so I need something fast to clamp the hi side.... Well maybe. I need to scope it once I think I got the low side taken care of.

 

[nieles]

i was looking through my collection of interesting app notes and found this one:

apt-0402 Eliminating Parasitic Oscillation between Parallel MOSFETs

nothing new or very spectacular but an interesting read.

 

[Arlo1]

Ok so I tried these from diodes.com as Nieles suggested I inverted the 5v signal from the hi side in hopes of when the hi goes hi it will hold the gate of the low off. But I had issues then I say the input for the new fet driver needed 12v or something close.. I'm kind of lost I need to sit and read the page some more because when I run it with 5v it tried not to allow more then ~6 v to the gate. Its to bad they are so small.

I should add the original goal was not to use them as they are intended.... So maybe the sink basically follows the input?

I also tried 10nf caps and IM sure they made the false trigger worse! I was seeing as much as 8v without turning the motor.

 

[zombiess]

Maybe time for a new driver with more features or incorporating discrete protection (I heard High hopes has experience doing it discretely) since your power level is going up.

 

[Arlo1]

Maybe time for a new driver with more features or incorporating discrete protection (I heard High hopes has experience doing it discretely) since your power level is going up.

I will be looking at different fet drivers for one of th enext revisions but the TD350 you guys are running wont work for me.

 

[Lebowski]

Why all this complex, excuse my language, nonsense ? What's wrong with some
simple 2186's with the gate resistor/diode combo and bootstrap supply
for the high side ? What is all this extra stuff for ? Adding extra drivers for extra
FETs etc etc will never work as the timing is just too critical and will probably
be just too fidgety and never work over temperature variations etc etc.

All you're doing is fighting the complications from a bad power stage layout.
If you need too many caps and tricks something is just not good, things like
that should just not be necessary.

Use the KISS oprinciple. Build 4 6FET stages. Use 2186's. I don't know how
many 6FET stages can be driven using one set of 2186's, but if it's less
than 4, use 2 sets of 2186's and parallel their inputs towards the controller IC.

 

[Arlo1]

Unfortunately things need to be more complicated as power levels go up. The extra fets are to help push more amperage thought the driver system for when I parallel lots of big FETs the driver chips will not handle it on their own.
I will be changing the driver design down the road but for now I'm going to figure this one out. Its a learning experience and I enjoy it. At the end of the day my current problem is from the miller effect which is not caused but the driver fets but can be solved with a more fancy fet driver with a clamp feature.

Lebowski I can put any driver in the system you want right now but non of them will change the miller effect. Only some can help combat it with a clamp future.
I also think is safe to say no matter what I choose there will be a bunch of people telling me to use something different this always happens. Truth is only few people have experience with the power levels I'm heading for so I have to push though and learn what I can from all of you. Sorry for being stubborn but I have had the parts to build this for almost a year and now I'm working though it. I see true value in this. It really is a black art and every time I figure out how to make it work I'm that much more wiser/experienced which is what I need!

 

[Lebowski]

I just have the feeling, you're trying everything to fight the FET killing spikes,
you're putting patch upon patch upon patch. But you're not addressing the root
cause of the problem...

 

[Arlo1]

I just have the feeling, you're trying everything to fight the FET killing spikes,
you're putting patch upon patch upon patch. But you're not addressing the root
cause of the problem...

Lebowski we are talking about 2 completely different issues. Last time it was to high of spikes on drain to source under load which is realted to cap placement and diode speed.
This time so far as I have not done hard load yet, its a miller effect which is to do with the gate capacitance and the speed of the switch on the opposite side of the H bridge.
I don't think the root cause in this case is the fet drivers.
In my last build this was not a problem so I continued to use the driver design thinking if the caps were in a better place I can keep the drain to source spikes under control.

I am using different fets and 1 more of them in parallel then last time as well I am using a different mounting technique.

I will re design don't worry. This is not easy stuff. Thing is IM truly on my own. I can learn from you guys but 20 guys will tell me to do it 20 different ways and NEVER will they agree with each other. So If I build it the way you say then highhopes will say that's not right and if I build it his way you will say that's to complicated etc.
I hope you guys understand where I'm coming from. My frustration is from to many people saying to do things to many ways. For now I will learn what this takes to make it run then I will learn what that is and move on to the next design.

 

[HighHopes]

you're doing fine arlo, don't worry. this is how we all learned. when you have a failure, try to understand it. where is the failure occur. under what conditions? so you have found it... there is a turn ON pulse when it should be held OFF. what could cause this? so you have found it by reading. then you understoodd the physics and it made sense so you are matching theory with bench test. good.

when others give their suggestions thats OK. take the parts that make sense, that match the theory, that match your bench test. narrow it down. ask questions "you suggest this, but the outcome would be that, why do you think it would work for my problem?". etc.

now read how others have solved miller effect and you generally find 3 solutions..gate emitter cap, bi-polar power supply, or clamp. so try some solutions and if it works then great, means your diagnosis was correct and that problem is solved. personally, i do not like gate/source cap because it has potential to solve one problem but introduce another. bi-polar is not practical for you because it is way too difficult to patch that.. even a clamp would be a bit of a hack, but is at least doable.

then you have new knowledge and the next time you design one of these you'll hold those thoughts in the back of your mind and decide if you need to exercise that experience or not. when you designed this gate drive did you thinkk at all "miller effect" ? probably you never heard of it. But i bet you'll think of it next time :wink:

 

[HighHopes]

as you go up in power, dv/dt increase and/or di/dt increases. these things are big sources of problems in mysterious ways. a bootstrap power supply with zero fault tolerance will only get you so far before its short comings are revealed. at some distance along the slippery slope you will find it more struggle and more struggle to keep a KISS gate drive working reliably as power increases.

as the system power level goes up, generally so too does the cost. eventually you might decide that $50 extra parts is worth the protection it offers to your $500 dollar system.

Here is my rule of thumb:
in my experience 1kW or less you can basically do what you want and it will work. even appnote style design can work just fine.

1kW to 10kW (i'm talking continous rated power) you have to start thinking about dv/dt and/or di/dt and start mitigating some of the problems that *MIGHT* be present in your system.

10kW to 50kW you must design for dv/dt and/or di/dt or you can expect failure. consideration to fault tolerance might be advisable because your systsem is getting expensive and also the application that required such high power might also need to Stay Running.. so designing in some (or all) fault tolerance can be worth it.

50kW to 100kW fault tolerance is absolutely necessary because risk of explosion & fire is real. also for sure the sytem cost more than $500.

 

[HighHopes]

i'm hijacking your post.. but if you don't mind one more item..

for zombies gate drive, i think his power was 1kW to 10kW. you might ask why i suggested so much fault tolerance and protection from dv/dt and di/dt when even by my own rule of thumb perhaps it wasn't fully warranted? my reasoning was that this product will be built with limited test equipment to validate design and debug, limited patience, and in the evenings on limited free time. i figured for the extra cost would be worth it if if lead to an IMMEDIATE working gate drive that did not require debugging. you could focus your time and efforts on the rest of the system and get out ripping around the track sooner. he was just building one, not a million. for some future gate drive you could take some features away that were not needed to reduce cost or just leave it and say it is what it is... a Cadillac.

 

[zombiess]

I need to do it justice now and actually finish building it. Its about 50% done. I am stuck on how to attach heat sinks and then put it in a case, that's at least 25% of what remains and I have no ability to do the needed mechanical work.

 

[Arlo1]

Thanks. Highopes. You have lots of good points. Yes that is a good plan for a driver design for Zombies the only reason I don't copy it is because I need higher PWM or I at least need to be able to test at higher pwm to find where this motor wants to run. I think in the future I will end up with more Low inductance motors to push my self to run.

So as I work on this one Its time to find a new fet driver and get the basic driver circuit analysed to see if we can get some people to agree on it. Its to bad digikey doesn't have quite enough search filters.

 

[Arlo1]

I need to do it justice now and actually finish building it. Its about 50% done. I am stuck on how to attach heat sinks and then put it in a case, that's at least 25% of what remains and I have no ability to do the needed mechanical work.

Its not always easy. But what I did was not to hard I am very lucky to have my shop and the welding shop 2 doors over and my work shop in the basement and the shop I work at most of the time and the university trades buildings where I work as well But the way I do it zombies is focus on a big heat sink and the little heat sinks then worry about a case later because you will want to run it a LOT with the cover off to scope it all.