patallen
1 W
I just added a second NAND gate from this century, still 4011 so not the best choice ever (a 74xx is on the go with 4ns prop delay), on the low drive so all the pwm outs are now "equalised" in time. There is a 30ns propagation delay from mcu to driver on all pwm outputs, low and high. So now the Ir driver wont know. This will just alter the whole timing from the hall signal to the final gate drive of 30ns+the hardware filtering process+ the software filtering process. Will measure that tomorrow to see how retarded it is. Shouldnt be much to worry about for now.
I also removed the pre-10 ohm resistor which seemed to reduce considerably the dt (now only 10 ohm per fets instead of 20).
Lets see how it gets to the fets...tomorrow...
This should make the whole thing more stable, plus it simplifies my code since i dont have to care anymore of the inverted logic of the low drive
well....4 less instructions...lol...
I also removed the pre-10 ohm resistor which seemed to reduce considerably the dt (now only 10 ohm per fets instead of 20).
Lets see how it gets to the fets...tomorrow...
This should make the whole thing more stable, plus it simplifies my code since i dont have to care anymore of the inverted logic of the low drive

well....4 less instructions...lol...