Post double-pulse test scope shots of your diy controllers

[Njay]

As the title says , post here scope shots of double pulse tests on your diy controllers/power stages. Let's see what's common what's not, compare notes...

Ok, I start! This one of the bottom IRF3205 from a simple H-Bridge which does synchronous rectification.

 

[zombiess]

Bump

I only see one pulse there (unless this is the in between shot).

Do you have access to a small Rogowski coil? I've been looking at some lately trying to decide if I really need one or more likely two for some of the work I'm doing.

 

[Njay]

It's in between, I just wanted to show the relevant data, behaviour of switching ON/OFF.

No I don't have any Rogowski coils, but that would be really, really interesting to have. There are ones you can (barely) put around a big FET's leg but I don't even want to look at the price (it's a "system as you probably know, the coil plus the integrator, where's probably most of the price).

 

[zombiess]

It's in between, I just wanted to show the relevant data, behaviour of switching ON/OFF.

No I don't have any Rogowski coils, but that would be really, really interesting to have. There are ones you can (barely) put around a big FET's leg but I don't even want to look at the price (it's a "system as you probably know, the coil plus the integrator, where's probably most of the price).

I've been looking, Athena Energy Corp has what appears to be the lowest cost option at $850 for the coil + integrator. I believe I'll need two for the work I want to do with current sharing. Not cheap, but it provides really useful data such as the switching energy.

From what I've seen another person post, the coil is only ~$150 USD, the bulk of the price is in the integrator just as you suspect

You might already know this, but going through it again helps me solidify causes in my head.
That turn off voltage overshoot is caused by the stray L in the MOSFET leads and PCB during the freewheeling diode turn on. If the lower MOSFET is turning off and the upper one starting to carry the freewheeling current, the overshoot is what sets up any ringing which is going to occur (looks like you have bout nada for ringing). It's the interaction of the stray L in the opposite side interacting with the Cds of the MOSFET which just turned off. Sets up a tank circuit.

I use to be puzzled by this and couldn't find a reason why it was happening on my first build, I think you may have commented on it as well. I've been experimenting with adding additional G-S capacitance (I'm up to about 22nF per MOSFET) to counteract it so I can maintain a fast switching time. The other option is to slow down the switch speed. You don't have much overshoot compared to what I've seen on my stuff. I'm just under 200ns, ~180ns switching 300-600A in single/double pulse tests with 3 parallel IRFP4568s. The cap resists the Cgs discharging and polarity reversal from the stray inductance field collapsing which pulls the G-S low with a dip at turn off which happens from the end of the Miller plateau to Vgsth. I've only seen this dip when switching relatively big current really quickly, but I've seen it enough times to figure out it's real. The G-S cap stretches out the time spent from the Miller plateau to Vgsth thus dissipating the effects which cause the overshoot. I'm not fully sure of all the downsides caused by adding the G-S cap beyond requiring higher gate drive current.

I keep trying to dig deeper and understand this stuff more.

 

[Njay]

From what I've seen another person post, the coil is only ~$150 USD, the bulk of the price is in the integrator just as you suspect

When you realize that the integrator has to deal with small diferential integration, you realize it's going to be costly . I actually suspect it needs to have some kind of regular "calibration/zeroing" during use.

You might already know this, but going through it again helps me solidify causes in my head.
That turn off voltage overshoot is caused by the stray L in the MOSFET leads and PCB during the freewheeling diode turn on. If the lower MOSFET is turning off and the upper one starting to carry the freewheeling current, the overshoot is what sets up any ringing which is going to occur (looks like you have bout nada for ringing). It's the interaction of the stray L in the opposite side interacting with the Cds of the MOSFET which just turned off. Sets up a tank circuit.

Yeah, you're steering current from one FET into the other. Current comes in from the motor lead to the PCB (or whatever your mechanical design is) and reaches a "T crossing", then going down (botton FET), through the stray inductances too; when the bottom FET goes OFF, current needs to stop flowing down and start flowing up, and the stray inductance "down there" isn't happy seeing all the current going away quickly, so it creates voltage to counter-act it. Then the ringing with Cds. That's my understanding too. The measurements on the graph above were done directly on the FET legs, with the short GND clip.

I use to be puzzled by this and couldn't find a reason why it was happening on my first build, I think you may have commented on it as well. I've been experimenting with adding additional G-S capacitance (I'm up to about 22nF per MOSFET) to counteract it so I can maintain a fast switching time. The other option is to slow down the switch speed.

On the layout, the top of the "T" must be as short & low inductance as possible, that is, the connection between the top FET's source (or drain if using P-FETs) and the bottom FET's drain.

You don't have much overshoot compared to what I've seen on my stuff. I'm just under 200ns, ~180ns switching 300-600A in single/double pulse tests with 3 parallel IRFP4568s.

I have N and P FETs on TO-220, so I could make the "T" connection using the heatsink, but it isn't much current, voltage and short switching time has you have. Would it surprise you if I said there is 2.5 inches between the DC link caps and the FET in that test above, without any additional snubber caps?

The cap resists the Cgs discharging and polarity reversal from the stray inductance field collapsing which pulls the G-S low with a dip at turn off which happens from the end of the Miller plateau to Vgsth. I've only seen this dip when switching relatively big current really quickly, but I've seen it enough times to figure out it's real. The G-S cap stretches out the time spent from the Miller plateau to Vgsth thus dissipating the effects which cause the overshoot. I'm not fully sure of all the downsides caused by adding the G-S cap beyond requiring higher gate drive current.

I keep trying to dig deeper and understand this stuff more.

I can't think about the effects of extra Cgs, but the entire switching event goes through several phases, some could be sped up if the driver was smart and not just the voltage source we use. On the other hand, in the quest for shorter switching times, there are also EMI issues to consider. Anyways, definitely fascinating stuff

 

[zombiess]

I've been studying the different phases to try and gain a deeper understanding.

I believe most of the RFI comes from the overshoot events and reverse/forward diode recovery. It's very deceptive on how much is actually going on in switching events. They are quite complex.

I'm concerned about the RFI/EMI that is generated. It's certainly a balancing act, but without the expensive tools to measure it quantitatively it's like shooting in the dark. I've read and been told that device selection plays a big role as well based on how the diode reverse recovery is, soft vs snappy.

I'm actually very curious to figure out more about adding a large G-S cap. HighHopes said he's used G-S caps but never anything near as large as I have. I've read some pretty complex methods to achieve the same reduced turn off signature that the large cap gives, but I haven't seen anyone talk about using just a cap. The goal with all of them is to extend the time it takes to turn off the region between the Miller plateau and Vgsth. Squashing the overshoot should significantly reduce RFI, but I'm not sure of the negative side effects. The positive side is reducing EMI from overshoot, faster switching times allow for lower switching losses with less ringing. That's two pretty big wins for only needing a larger gate drive power supply. I'll find the catch sooner or later, but so far everything looks good on the scope.

Here are some shots showing the dip with and without the G-S cap in place. These were either 300A or 500A shots with 3 parallel IRFP4568's.





I'm not sure about your DC Link question as I have limited experience myself.

I do have this one thing going on that I haven't sorted out. With single pulses my waveforms look text book, but with repetitive pulses I get all kinda of garbage at the Miller Plateau like this. In operation the D-S transition looks clean without ringing, but the G-S looks sloppy. Slowing things down, removing the G-S cap doesn't seem to make much difference when the signal is PWM. My 1st controller did the same thing and I've scoped other controllers like the common Xie Chang which switching super slow and still show signs of this. Should every transition look clean showing the Miller Plateau? One thing I find odd is if I am zoomed out and make a capture, then zoom in, the G-S looks clean. If I zoom in and then capture I start seeing the stuff pictured. Thoughts?

This picture is only representative of what I see, my actual D-S transition doesn't have this much ringing.
View attachment 2

 

[Njay]

The ringing Vgs switching on reminds me of this. The green graph is "Vgs" measured but before the gate resistor (the yellow is the real Vgs). Measuring with probe ground lead or far from the FET also gives waves with deep ringing.

 

[zombiess]

I'm going to break out my differential probe and check it again. Might try dropping the gate resistor from 6.2 to 10 ohms as a test. I want to be sure before I put this thing in it's case and try riding it.

 

[Njay]

See 16 0nf_vs_68nf_ds_200ns_off.png . The time the current takes to turn off is the width of the top of the big lump (from when Vd starts to slow down, can't be seen exactly in your shot) on the green wave (the 1st lump) - the period marked red in the pic below. What if the red time is being replaced by the yellow time? This gives higher switching power dissipation. Are you sure you are switching faster with the g-s cap?

 

[zombiess]

See 16 0nf_vs_68nf_ds_200ns_off.png . The time the current takes to turn off is the width of the top of the big lump (from when Vd starts to slow down, can't be seen exactly in your shot) on the green wave (the 1st lump) - the period marked red in the pic below. What if the red time is being replaced by the yellow time? This gives higher switching power dissipation. Are you sure you are switching faster with the g-s cap?

I'm pretty sure it's not dissipating more, at least based on the papers I've read an my understanding of what causes this resonant peak. That overshoot is energy from the turn on of the freewheeling diode + the stray L in the leads + PCB. The energy has already been put into all those components so the trick becomes slowing down it's dissipation over a longer time. How quickly it's switched also has dramatic effect, slower of course = more energy lost but less overshoot/ringing.

Without the G-S cap in place I'm limited on how fast I can switch because of ringing and overshoot (which are of course related). I also get a big dip on the G-S as can be seen in the one picture after hitting a certain switch speed threshold. This dip coincides with the resonant peak and is caused by the intrinsic Cgs capacitor being discharged by the Cgd charge reversing polarity from the overshoot over the bus voltage like in this picture. Without additional Cgs I might only be able to switch at ~300ns but with added Cgs I can switch at 180ns and still maintain lowish RFI which would normally increase with faster switch speed. I haven't tried hitting so fast that I can clip the Vgs down to 0 yet, but this pic is pretty close. Have you ever seen this effect before? Mind trying to reproduce it?


This dip doesn't appear until a certain switching speed is reached and I'm not sure what the relationship is yet, but from experimenting I can tell it's tied to switching speed because once the threshold is crossed the bugger shows up as a dip on the G-S at turn off. I've yet to see any documentation on this effect so I'm going with my own understanding. Since Cgs has it's charge reversed, the stray L that's tied to it also has it's polarity reversed from the initial start of turn off. When Vgs(th) is reached that stray L + the opposite diode turn on energy discharges its field and interacts with Cgd which causes the muted ringing seen after the overshoot. I think the turn on the the freewheeling diode energy might work to counteract some of the stray L once the bus voltage is exceeded since I believe it's charge is opposite (I'm not sure on this part). I also think there is a reverse recovery event that happens at the turn off of the switching MOSFET since it's body diode now needs to block.

I believe once the point of having Cgs get pulled negative is reached is when ringing starts to get out of control and needs additional attention. I've been asking how much ringing is too much and haven't received and clear guide lines other than being told my ringing is well below what is considered acceptable. Maybe too much is some point just before overshoot starts pulling G-S negative?

So much happens in a single commutation that it's hard to keep it all sorted out what effect what. Then it gets more confusing with hard/soft switching (ZVS/ZCS). I'm still trying to make sure I keep it all straight. I'm at the point where I'm starting to dig into the physics of the silicon / carrier types to understand better.

BTW, I double checked my switching events on my inverter at ~150A and every pulse looks clear and no longer appear like the example shot I posted. Time to button this thing up and test it under load I also hope I got my explanations correct, it's still easy for me to get mixed up

 

[Njay]

I'm pretty sure it's not dissipating more, at least based on the papers I've read an my understanding of what causes this resonant peak.

I guess you don't have a way of measuring the drain current during the switch.

That overshoot is energy from the turn on of the freewheeling diode + the stray L in the leads + PCB.

I don't know what is that "diode turn-on energy".

Without the G-S cap in place I'm limited on how fast I can switch because of ringing and overshoot (which are of course related). I also get a big dip on the G-S as can be seen in the one picture after hitting a certain switch speed threshold. This dip coincides with the resonant peak and is caused by the intrinsic Cgs capacitor being discharged by the Cgd charge reversing polarity from the overshoot over the bus voltage like in this picture. Without additional Cgs I might only be able to switch at ~300ns but with added Cgs I can switch at 180ns and still maintain lowish RFI which would normally increase with faster switch speed. I haven't tried hitting so fast that I can clip the Vgs down to 0 yet, but this pic is pretty close. Have you ever seen this effect before? Mind trying to reproduce it?

I currently don't have the controller with me to test, but I use simulation alot to understand and predict effects. So far I'm unable to reproduce your Vds waveform with the Cgs cap added, the effect I see is that the parasitic oscillation dies quicker, and Id goes to 0 a little faster. The lump doesn't go away, and the dip you see is actually a bump - unless you measure Vgs with the reference GND at the FET driver (measuring a few nH from the FET's "real" source), then the signal is the bump's symmetrical, a dip (in the sim below there's only a total of 6nH between driver GND and FET source).

(...) it's still easy for me to get mixed up

Ahhh, if it were only you I'd be ok

 

[zombiess]

My measurements are all made at the MOSFET legs.

Interesting that you get a bump vs a dip. I too get a bump, but only when using a differential probe. Using a normal probe I get a dip which is what I would expect given my current understanding of operation. I never thought about the role inductance plays whrn measuing it. Now I'm wondering if the dip is proportional to the lead + pcb inductance. I'm just barely starting spice sims, but I don't think they model the lead inductance.

Turn on energy is area of the overshoot that is seen when a diode switches from reverse bias back to forward bias. It's reverse recovery's twin and in some cases it can dissipate more energy than reverse recovery. There are some good manufacturers literature on this. I usually find it reading on SiC devices.

 

[Njay]

My measurements are all made at the MOSFET legs.

Including a really short GND path from FET source to probe, right?

Interesting that you get a bump vs a dip. I too get a bump, but only when using a differential probe. Using a normal probe I get a dip which is what I would expect given my current understanding of operation.

To me it makes sense to see a bump, because the inductive parasitics connected to the FET drain will up the voltage at the drain when the current starts going down, which capacitively couples to the gate, adding to the Miller plateau. But see next.

I never thought about the role inductance plays whrn measuing it. Now I'm wondering if the dip is proportional to the lead + pcb inductance.

It is proportional to lead+pcb inductance and to where you put your probes. This is the circuit I used for the sim above. You now have light green, rose and dark green for "Vgs", being that the difference is that the GND of the probe is respectively at the sillicon, midway the parasitic inductance between the sillicon and the driver GND, or at the driver GND. As you see, we went from a bump to a dip. And look 'Ma, almost no gate ringing when the probe is mid-way.


But this is still simulation. The question is, how much inductance is there between driver and FET in real life? It is however useful to provide some insight on the effects of stuff.

I'm just barely starting spice sims, but I don't think they model the lead inductance.

They don't, you need to model it yourself.

Turn on energy is area of the overshoot that is seen when a diode switches from reverse bias back to forward bias. It's reverse recovery's twin and in some cases it can dissipate more energy than reverse recovery. There are some good manufacturers literature on this. I usually find it reading on SiC devices.

Thanks, I'll have to go read about that.

 

[zombiess]

Here is my double pulse test

 

[Njay]

No gate waveforms ?...

 

[zombiess]

No gate waveforms ?...

I got them, just not in a pretty composite. Here they are. The yellow trace is the current sensor. As you can see I'm picking up radiated noise almost certainly from the load coil since it's only 6" away. Short ground vs long ground = almost no difference, same with the differential probe which has an amp that picks up the coil noise / EM. I narrowed it down and figured out how to minimize it by positioning it more carefully. 60V @ 233A peak is a probably a decent size EM pulse.

1st pulse on


1st pulse off


2nd pulse on
View attachment 3

2nd pulse off


Zoomed out double pulse with DC battery current in yellow, ~6.4A/mV


This is comparing the turn of of a 10 ohm gate resistor vs a 6.2 ohm. They have about the same amount of noise so I stuck with the 6.2 ohm for lower switching losses. This one shot was very informative for me since the noise stayed the same. I feel like I'm really starting to relate where different ringing / noise is coming from. Got some fancy math formulas I can use to calculate the layout/lead inductance from measured ring frequency by just adding some temporary small extra Cds capacitance and using the delta of the ringing freq. Should be a good way to help in objectively evaluating different layout designs.

 

[Njay]

Do you have any with both Vgs and Vds?
Interesting how your current on the 2nd pulse is comming down in "arc". Hit your sensor's current limit?

One thing I noticed once, is that I have to connect the GND lead of *unused* scope channels to the GND of probes on channels I was using, in order to completely remove interferences. Looks like unsed probes cabling/GND leads can force noise into the channels being used (when using 2 or more probes, all probe GNDs must also be connected).

 

[zombiess]

What do you mean by coming down in an arc? The fact that it doesn't just go to zero when the pulse ends? That coil really rings. Ignoring the spikes the current sensor is topped out during the 2nd pulse. It's maximum output is 2.48V above the reference voltage, I'm AC coupled in those shots.

I didn't make any Vds vs Vgs shots. I could do that tonight before I put everything into a case so I try tuning the controller and testing under load. I have to do a final once over of all the gate drivers any ways.

What do you think of the shots?

In the 2nd to last shot I'm puzzled by the wavyness of the pulse on Ch2. The sines on the current and voltage are out of phase by > 90 degrees, looks like 100ish. What could be causing that, shouldn't current and voltage be in phase or is this the time it takes to establish the initial flux field in the inductor?

 

[Njay]

Hey, nice, thanks . I was referring 2nd pulse current coming down in an slight arc and not straight, but now you already said you topped your current sensor, explained.

I don't know exactly what to think about the shots, they are at way higher current I've ever tried. The crazy current ringing at the commutation points I also see in my tests (I'm using a shunt since it's low current), no matter how much current I'm switching.

I find weird your "1st pulse on", roughly no Miller plateau, which I think should be seen clearly because there's no current at that time, but maybe that's because of the super fast switching (Miller zone so fast it isn't seen).

Zoomed out double pulse with DC battery current in yellow, ~6.4A/mV

I think you meant 6.4mV/A here, ~234A.
The current is ringing badly on turn off here (the 2nd to last you mention), it looks like your DC link caps are resonating a bit with the power input wiring ("battery" wiring). I have no feeling for how "worrying" that is, I've seen it only in simulation, when there's not enough DC link capacitance, or too much wiring inductance (depends on how you want to see it ) - disadvantages are that current is going back-and-forward to power supply (probably also creating noise on the battery wiring, have you ever scoped the Vbat+ at the controller's input?) and it increases the RMS current on the caps, but you have caps with big RMS current ratings.
I guess ringing frequency should change if you twist the power input cables (or run them next to each other, or anything that reduces inductance on that battery-controller loop).

 

[zombiess]

Thanks for catching the unit error, you are correct with 6.4mV/A.

The small miller plateau is due to the G-S cap. It's still there but it's hidden a bit in the oscillation and it's also smaller due to the G-S cap.

I get the impression that the commutation point noise is just that, noise from the switch event being conducted. My probes can pick it up if they are close enough. The differential amp is super sensitive to EM since the one I have is not designed for this type of work. I need to eventually get a proper HV differential.

When I'm single/double pulse testing a half bridge there is stuff all over the place, current and voltage. The current wave form oscillation you see is the coil ringing. I verified that by altering it's value between 5uH, 25uH and 30uH. I also tried a 120uH and a 400uH coil. The frequency of oscillation changes in each case.

I tried scoping the voltage on the DC Link, but it's useless because with the setup I'm using the voltage just bounces around all over the place. I'm not sure if this is normal or not. I know I'm using some pretty high currents into really hard to drive loads. Kinda jumped off the deep end, but my bench time has been very informative and I've connected several dots that needed connection.

HighHopes has said not to sweat the pulse tests too much and don't take them too seriously as several things happening might not be there under 3 phase SVM or even under normal load. He said to look for really bad bad things and bad performance in the test. Not quite sure what that is yet, but I think I'm starting to get a feel for it. I'm told a lot of this stuff is done by feel and I think I understand why since I think I'm starting to "get the feel". It's neat to be able to identify what causes each ringing issue.

I have some scope shots showing D-S and G-S on the shot, I need to edit them together an post them up. Figured I should get them for documentations sake.

With this layout I'm seeing everything I saw on my first controller, but on this one everything is more controlled, less ringing and I'm pulse testing with much more current than I was on the first design.

 

[Njay]

Ok. This is a old shot of the current commutation, around 15A at the end of the cycle (yellow trace). Also lots of interference at the comutation points.


As for the ringing, ok, it's your coil. I never saw anything similar; my shunt is between DC Link caps and FETs so I can't watch battery current but would see regenerative current. Anyways, I'm not playing at your current levels. I use the motor with the rotor locked for the tests. The double pulse on the 1st post was taken like this.

 

[Co Aung]

Hey guys, i would like to ask for help how to remove the sudden charge up of capacitor at the start of the first pulse?

 

[zombiess]

Hey guys, i would like to ask for help how to remove the sudden charge up of capacitor at the start of the first pulse?

Could you elaborate a bit more?