Finite-element thermal sim is of course the most accurate, for a relatively simple case like a controller you can construct a simpler model for rough estimates. Simple thermal models are
exactly analogous to an electric circuit for analysis.
Power flow is represented by current, and temperature is represented by voltage. Ohm's law is still valid, but now R=V/I gives us units of C/W - thermal resistance! You can even get really fancy and simulate transient behavior with capacitors. You'll see this on FET datasheets sometimes.
Anyway, you can just construct a circuit based on the heat flow paths. It's easier if you have a SPICE package, but you can calculate by hand too. I put together a simple model for a 12-FET controller:
The voltages shown indicate the temp (rise over ambient) at each node in the circuit. The topmost set of voltages, right under the current sources, would be the FET junction temps.
I assumed a total power dissipation of 60W as a ballpark figure, divided to 12W per each high-side bank and 8W for each low-side. The power loss is represented by current sources. Each FET has a resistor which represents the total junction-to-case and case-to-sink resistance, which is about 0.9 C/W for the 4110-type FETs. Another resistor in series represents the isolation pad, which I'm estimating at 1 C/W. The two FETs of each bank are connected in parallel.
Here it gets a little fuzzy. In the ideal model, the heatsink would be a uniform temperature (represented by a single node) with the sink-to-ambient Rth represented by a single resistor. However, the controller's power dissipation is distributed across the entire sink and there are likely to be slight temperature differences. So, I modeled this by dividing the heat sink into several parallel resistances, separated by small resistors which represent the spreading effect within the heat sink. This model assumes a total sink-to-ambient resistance of 1 C/W, which should be roughly ballpark. This approximation doesn't affect the outcome very much.
The model shows the FET junctions varying from 67-72 deg C above ambient. That is a reasonable result and well within specs. Obviously the low-side FETs are slightly cooler since they are dissipating less heat here.
The more interesting and relevant result comes if you look at the net junction-to-ambient Rth for each of the FETs. You might assume that this is equal to the sum of the resistances: junction-case, case-sink, sink-ambient, which would be 0.9+1+1=2.9 C/W. That's valid if there's only one FET on the sink, but totally invalid when there are 12 FETs on the same sink. Using the numbers from the model, each high-side FET dissipates 6W and is 71.5 C above ambient, so Rth = 71.5/6 = 11.9 C/W! For the low-side FETs, Rth = 67.7/4 = 16.9 C/W!
Since the sink is dissipating 60W, at 1 C/W we'd expect about 60 C delta across the sink, which is exactly what the model shows. From the sink to junction at the left-most FET bank is 71.55-60.15 = 11.4 C, which at 12W means 0.95 C/W, which is exactly equal to the parallel Rth's of the two FETs. It's a surprising result, but everything is behaving as it should.
This shows why we can never dissipate as much heat as we think we should be able to!
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