Unstable phase behavior above 60 V on custom VESC-based hardware

[ponp33]

Hi everyone,
I’m new on the forum, so hello everyone!
I’ve been reading many of the very technical and interesting posts here, and it motivated me to join and ask for help with an issue I’m facing.

I’m working on a custom ESC hardware design, very similar to the VESC 75/300, running a custom-configured VESC firmware.
Most of the design follows the open-source VESC 75/300 schematic, with the following differences in the power stage:

• 4× IRF7769 MOSFETs
• Rgate = 4.3 Ω
• Gate-drive circuitry mostly unchanged

Up to 60 V battery voltage, the ESC works very well (the curve look clean and stable phase current)
Here is an example of the normal waveform:



same with higher current:



But above 60 V (target is 75 V), the ESC becomes very unreliable.
Sometimes it runs correctly, but most of the time the phase currents behave strangely or the motor fails to start.
Here is an example of the abnormal waveform:

when if run almost well:

And when it actually run but become very noisy (most of time)


a correct detection using VESC 100 250 MKIII gave those values:

I’ve already tried adjusting:

• observer gains and types (mxlemming and ortega)
• current controller kp / ki
• motor parametrers

…but with no improvement. I’m unsure whether the issue is caused by:

• hardware limitations (MOSFET switching, gate resistance, high-voltage behavior)
• PCB layout / noise
• or firmware tuning

The fact that the motor sometimes runs almost correctly gives me hope that it’s just a matter of tuning the FOC parameters, but I no longer know where to start.

My main question:
Has anyone experienced a similar issue on custom VESC hardware becoming unstable when increasing voltage, and did you manage to solve it?
Any suggestions on what to check first (gate-drive tuning, deadtime, shunt filtering, DRV settings, observer tuning, etc.) would be greatly appreciated.

Thanks, and I’m glad to join this community!

 

[mxlemming]

Looks like the current is getting stuck around zero, I have seen this happen due to excessive dead time, but never to this extent. Perhaps check for correct switching on the phases? Are they always PWMing properly, with nice square waves? Are your drivers UVLOing?

Try reducing the inductance. This often helps the observer stability, but I think this is likely a hardware issue...

 

[amberwolf]

4× IRF7769 MOSFETs

Per bridge?

Are they genuine, from a reliable known source? (there are a lot of counterfeit parts out there, which may (mis)behave very differently from the real thing, especially as they near the spec limits of the real parts, which may be far beyond what the counterfeits can do).

(keep in mind that I don't know the VESC controller itself, just some specifc electronics components / behaviors).

 

[ponp33]

Thank you very much for your answers.
@mxlemming I already tried reducing the inductance; it seems to help a bit, but definitely not enough. I will check the PWM configuratio, I haven’t tested it at this voltage yet.

@amberwolf Yes, it uses 4 MOSFETs per half-bridge (4 high-side and 4 low-side), sourced from Mouser. I assume it’s a reliable supplier.

 

[AdR]

Mouser is a supplier. not a parts manufacturer. Are you sure bout the Rgate resistance.. seems a bit high

 

[amberwolf]

@amberwolf Yes, it uses 4 MOSFETs per half-bridge (4 high-side and 4 low-side), sourced from Mouser. I assume it’s a reliable supplier.

Generally, yes.

I don't have any other relevant thoughts, if all the hardware is following the original design. If anything isn't, then the only other thought I had was the gate drive--The FETs might not turn on fast enough or hard enough under some conditions if the gate drivers don't have a high enough current output, either because of the actual driver, or because of the gate resistors themselves, vs whatever the specific FET youv'e used requires for the given conditions.

 

[ponp33]

Thank you for your answers. I'm waiting for a harware with added footprint in order tu tune the gate drive path (diode for assymetric charge and discharge path). The porototype which gave curves a previously sent is dead . I'll keep you informed.

 

[ponp33]

Hello, my new board arrived today. I modified the gate control stage in order to have more tuning options. I based it on the official 100_250 VESC design, with separate charge and discharge paths (using a diode), and I added a 10 kΩ resistor between gate and source, as well as a TVS diode.

My board is made of two separate boards, and during early assembly I accidentally damaged some MOSFETs. This is why I added the TVS diode, mainly as protection against possible gate ESD when the power stage is not yet connected to the gate driver board.

With this new gate circuit, the ESC now works at 75 V, which is a big improvement. However, I am now facing a kind of saturation phenomenon. I tested immediately without the TVS diode, but the behavior is exactly the same.

When I increase the current command, the issue starts around 30 A. I can push it up to about 40 A by increasing the PLL gain from 2000 to 3000 (no clear explanation, just experimental testing to find an influential parameter).

The problem is a bit different now, so I’m wondering if anyone has an idea what could be causing this behavior.

 

[ponp33]

Hello, just to add that the gate voltage looks really clean, even though the behavior is strange. I’m currently stuck with this issue.