How do youi calculate phase amps? Do you use the 3 shunt currents? Why did you needed measurements for the PCB? Did you looked at the values of the shunt resistances and those of the operational amp (to calculate the gain).
How we calculate phase amps
The board measures current with low-value shunts in each phase (marked R006 → 6 mΩ).
Each shunt’s tiny voltage drop is amplified by an op-amp (MCP6021). The op-amp has a feedback network: Rf ≈ 10 kΩ (code “01C”) and an input resistor Ri ≈ 220 Ω (common on these boards), so the gain ≈ 1 + Rf/Ri ≈ 46.5.
The amplified voltage goes into the MCU ADC (12-bit, 0–4095 counts, Vref 3.3 V).
The physics chain for one phase is:
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ADC_counts → V_adc = (ADC_counts / 4096) * 3.3 V
V_shunt = V_adc / Gain
I_phase = V_shunt / Rsh = [ (ADC_counts / 4096) * 3.3 ] / (Gain * Rsh)
With Rsh = 0.006 Ω and Gain ≈ 46.5:
1 A at the phase ≈ ~0.279 V at the ADC input.
That’s ~346 ADC counts per amp (12-bit).
Inverse slope: ~0.00289 A per 12-bit count.
Sampling: we trigger the ADC mid-PWM (center-aligned) so we avoid switching edges. We read U, V, W, subtract a zero-current offset learned at idle, and then compute a magnitude (for protection/display). Today we use max(|IU|,|IV|,|IW|) for a cheap, conservative phase magnitude. (Later we can do αβ or RMS if needed.)
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Do we use 3 shunts?
Hardware: yes, it’s a three-shunt design (one per phase).
Firmware: we sample all three around the PWM center. If we ever only got two in one trigger, we could reconstruct the third as Ic = –(Ia + Ib), but on this board we can read all three.
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Why we needed PCB measurements
Because the counts→amps scale depends on real parts on your board:
Shunt value (R006 = 6 mΩ).
Op-amp gain (set by Rf/Ri).
ADC reference (3.3 V) and effective bit-depth (we sometimes map to a legacy “10-bit step” scale used elsewhere in OSF).
If you guess any of these, your amps are wrong by that factor. That’s how people end up “current-limiting” at the wrong value or blowing FETs—they’re driving blind.
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What I actually did in firmware
We keep the existing OSF convention that 1 “10-bit step” ≈ 0.15 A, because other code already expects that.
From the hardware slope above, we added a fixed-point factor so 12-bit counts map into those 10-bit steps:
steps10 ≈ (counts12 * 39) >> 11 (≈ counts12 × 0.0190)
That preserves all existing limits (e.g., 333 steps ≈ 50 A phase).
We also do idle offset calibration (average several hundred samples with PWM off) so “zero amps” is actually zero after bias.