36FET TO-247 Water Cooled Design for your review

[zombiess]

This is a 24 FET water cooled power stage with current buffered FET drivers I've been working on while on vacation. It's designed to be driven from either a DIY controller or an EB312 controller. I'm planning to run mine with an EB312 controller for testing purposes. This is my initial design and I'll freely admit I'm no power design guru so if anyone wants to chime in on anything bad I did design wise please feel free to do so, but make sure you explain why what I did was wrong.

The board design was done with wide traces to allow me to add lots of copper (mostly to the bottom side) to handle the extra current that will be required. Phases A/C are double sided with a bunch of vias added to link them, figured it was a good idea since I had the board space that more surface area = better for current sharing and heat sinking.

I added a lot of room for up to 6 capacitors for the phases and holes to connect the cycle analyst to the shunts. I also installed positions for up to 6 shunts to help cut down on the heat and off load it from the driver board if you plan to use an EB312 board like I am. I also just realized I forget a few extra connections to link the power and ground to the EB3XX controller board which I'll have to add on before having these made, so there is one error already LOL.

The Battery+ and Ground are setup for 6 gauge wire and has space for two large input capacitors. The phase wires are setup for 8 gauge wire.

Each water block holds up to 12 FETs each and has 3 holes running through them lengthwise designed to be tapped for standard 1/16 NPT threaded fittings. The design is to clamp the FETs between plates with 6-36 hardware for now. Eventually I will probably re-size some of the holes and have them threaded

Driver board layout is not displayed yet as I am putting them on separate boards until I'm sure everything is going to work, that way if I can keep it modular in case I goof it up and keep the initial design cost lower (don't think I've ever had a first run board be perfect). Connection to the power board is going to be made through twisted pair wires, this greatly simplified the board layout vs including the drivers on the same board.

Please post any comments/concerns/tips you have on this setup, aka have I done any major no nos in the board layout.

This board will not be built until I test my 12 FET block made from the ram cooler in mid Jan, starting small first to keep the costs down from mistakes. I'm also looking for enclosure ideas. I was thinking for prototype design I will probably put it in a plastic case with the driver boards and control board. Won't be the smallest setup, but should keep it short proof and easy to work on.

Thanks,
Jeremy

 

[circuit]

Why so many fets?

 

[hillzofvalp]

Looking to do 500-800A continuous with 1.8kA bursts?

 

[Electroglide]

Interesting solution for buffering the outputs of the IR2110's. Just an opinion, but I think that you should incorporate a method for adjusting the turn-on/off time of the power mofets via your driver. Should your buffer be too good and you have incredibly fast rise and or fall times, you will have issues with the Vds overshoot possibly causing avalanching and or miller induced gate blips causing shoot through. If you can adjust the turn on/off time, then you can tune your switching to give the best compromise for your layout. Do nothing, and you run the risk that it will blow up at one or more points in your operating area. Good to see that you have the individual gate resistors. One warning about the IR2110's or any older generation IR driver. The highside driver will latch if the digital input signal width gets too small. This can happen if you are using newer generation dsp's like the piccolo from TI with high resolution pwm generators. IR does give the minimum pulse width in their spec on their datasheet, but they don't tell you what happens when you violate that timing :lol: The worst thing about that is you could have a blow up that is not directly related to your design of the pcb board but to using one of the components outside of spec. That is a very hard failure to diagnose, especially on a prototype with no history.

 

[zombiess]

Why so many fets?

24 isn't that many, I was thinking about starting at 36 FETs because designing that board is much easier, but etard is only making two blocks right now for me to prototype with.
See the below quote from hillzofvalp VVVVVV

Looking to do 500-800A continuous with 1.8kA bursts?

My conservative estimation says that if I keep the Tc (Case Temp) below 70C I can sustain 360 phase amps with 20khz 90% DC @1uS on/1uS off stalled motor condition (thanks for the calcs Electroglide). I'm assuming that 4 FETs in parallel is more like 3 FETs for the calc. But yeah, basically a mini monster controller capable of driving just about anything and most of all, a reasonable price.

Interesting solution for buffering the outputs of the IR2110's. Just an opinion, but I think that you should incorporate a method for adjusting the turn-on/off time of the power mofets via your driver. Should your buffer be too good and you have incredibly fast rise and or fall times, you will have issues with the Vds overshoot possibly causing avalanching and or miller induced gate blips causing shoot through. If you can adjust the turn on/off time, then you can tune your switching to give the best compromise for your layout. Do nothing, and you run the risk that it will blow up at one or more points in your operating area. Good to see that you have the individual gate resistors. One warning about the IR2110's or any older generation IR driver. The highside driver will latch if the digital input signal width gets too small. This can happen if you are using newer generation dsp's like the piccolo from TI with high resolution pwm generators. IR does give the minimum pulse width in their spec on their datasheet, but they don't tell you what happens when you violate that timing :lol: The worst thing about that is you could have a blow up that is not directly related to your design of the pcb board but to using one of the components outside of spec. That is a very hard failure to diagnose, especially on a prototype with no history.

Thanks for the tips, I don't think I have to worry about latch up running it from the EB3XX 12 FET controllers as the driver, nice slow switching speeds. I installed the positions for the individual gate resistors so that I can tweak the switching speeds because the app note warned about VS overshoot (ultra fast turn off times) happening due to the super fast switching created by using the buffer.

I'm staying away from designing my own controller and will stick with the Xie Changs and add on to them for now, but I figured this might be good for anyone else wanting to get nutty.

So do you think my board layout is acceptable or does it need some tweaking to be better?

 

[bigmoose]

I like it! Two suggestions:

• DO NOT use a separate gate resistor for each FET. One gate resistor for the bank. In very special cases if you get into problems with high frequency oscillations you can split the gate resistors with 65% in one resistor and 35% in individual gate resistors. You likely won't need to do this.
• Be sure to plateau match the FETs in each bank. Search for texaspyro's instructions on this. He gave away a huge bit of knowledge in his post on matching FETs for his welder. We should thank him for that explanation byh following his advice.
• Add two inverter rated caps from rail to rail at the ends of each bank.

Other than that, go to production. The rest has to be worked out real time. Glad you are buffering the 2110's. Good move! You can get a nice Pchannel and Nchannel in one SO-8 package that works well. I'll share a hint here, go for 100V rating, not because you need the volt rating, but because you DO NOT want the lowest Rds on in these driver FETs. Too low Rds on and they ring.

 

[zombiess]

Just talked to etard, we are going to change the top two holes to a single centered hole to simplify things. I'm hoping he can machine both the top and bottom holes to 0.332" so I can use 1/8" NPT fittings. Right now the holes are setup for 0.240" which is 1/16" NPT fittings but he mentioned the we could have clearance issues on the top with the hex part of the fitting, I over looked that... ooops. Glad he caught it before starting.

 

[zombiess]

I like it! Two suggestions:

• DO NOT use a separate gate resistor for each FET. One gate resistor for the bank. In very special cases if you get into problems with high frequency oscillations you can split the gate resistors with 65% in one resistor and 35% in individual gate resistors. You likely won't need to do this.
• Be sure to plateau match the FETs in each bank. Search for texaspyro's instructions on this. He gave away a huge bit of knowledge in his post on matching FETs for his welder. We should thank him for that explanation byh following his advice.
• Add two inverter rated caps from rail to rail at the ends of each bank.

Other than that, go to production. The rest has to be worked out real time. Glad you are buffering the 2110's. Good move! You can get a nice Pchannel and Nchannel in one SO-8 package that works well. I'll share a hint here, go for 100V rating, not because you need the volt rating, but because you DO NOT want the lowest Rds on in these driver FETs. Too low Rds on and they ring.

Thanks a ton for your input bigmoose!

I wasn't sure if I should use a single resistor per bank or use individual resistors so I figured I'd draw it out with each one having a resistor, but what I'll do is redesign it with each gate connected per bank and then cut the traces if I need to make a change to the resistors.

I'll have to read his instructions on plateau matching as I've never heard of this.

What do you mean by adding inverter rated caps rail to rail at each bank? You'll have to clarify this a little for me. Right now I have 1uF non polar polypropylene 275VAC caps on the high side MOSFET banks to ground, C4A, C4B and C4C. Please treat me like I'm a goof and don't understand, it will help me get it right.

I've seen the complimentary packages and read the app notes many times, they mentioned the same thing about having too low of an RDSon on the current buffer because of the ringing, so I went with exactly what they mentioned in the app note, complimentary IRFD9110 and IRFD110 FETs that have a 100V rating and RDSon of 540mOhms/1.2 Ohms. I'm sticking with through hole components for now for troubleshooting / simplicity of design. The next version will most likely be more compact and I'll probably venture into SMD for the first time.

Unfortunately I'm far from an electronics whiz, but I can usually wing it by reading spec sheets carefully and following app notes / examples and assembling things together with some general electronics knowledge and then some empirical testing.

 

[bigmoose]

Zomb, don't downgrade yourself and your understanding, you have done a great job here! Let me go to the next level and try to help. 2/3 rd's of your layout rocks. The phase where you split the FETs and put 2 on each long bus, well isn't the best and needs to be redone.

Frankly your layout is frighteningly similar to one of my preferred ones. I have to reverify my on site encryption and IP segregation to make sure I didn't "let it out"! (Luke hate's the business model I am forced to labor under... it is so oooold school, as he would say, but it is what it is!)

Ok, humor aside. You will be better off going with Three SYMMETRICAL phase blocks. Make them all the same, in other words. You will have problems with the split phase, no doubt in my mind.

Think of your electrolytics as "bulk caps" to handle the ripple.

These (1uF non polar polypropylene 275VAC caps) are the ones that will save your FETs. I have two brands and types that I like, Sprageu 735P 3uF are nice, (datasheet http://www.vishay.com/docs/42093/v735p.pdf) and when I need to go cheaper, I recycle Aerovox RBPS 2.0uF/K1000Vdc Inverter rated caps off of larger 3 phase induction motor Vector Drives. For this type of diddling you can buy them surplus, but source new ones for production needs. The Sprague's have to be bought new, I have never found a secondary source.



Now if you want to make the "big leap" These caps MUST go at the end of each phase group across the rails. The Sprague 735's in 1 to 3 uF package very nicely if you cut a hole in the PCB and solder the tabs to the rail bus bars. ..kr_p I'm giving too much away, corporate says... "shut up, I say, I am corporate..."

All successful high power designers have to change their thinking about the Wicked Infitesimal Resistance (Imedance) Element = WIRE. It HAS inductance. You need to run the numbers yourself with realistic estimates of dI/dt and see how large a bounce you are going to get. Ask Luke, he and I did a little noggin nocking a few years ago when he was pulsing a A123 pouch at 300 amps, he was getting IIRC, a hundred plus volt spike, on a few inches of copper bus bar. I think I made a believer of him.

So, revise your layout for 3 legs, put 6 Inverter Rated Caps (They will have TABs and not wire leads), one on each end of the water block, and across the rails. Stick the bulk, ripple electrolytics where ever they fit.

Ok, corporate won't let me show the final design, but this was an early rejected one. See how close they are? You want to mimic the upper block layout. This was with the Aerovox RBPS 2.0uF/K1000Vdc Inverter rated caps, the Sprague packaged better.



Ok, on plateau matching. You do not want one FET to come on before the others. It will pop like popcorn. That is the secret of plateau matching. There can be variances bank to bank, but each bank must be somewhat matched. FETs from the same lot and tested like texaspyro said. Basically you put a fixed, specific voltage between the gate to source and put a load resistor on the drain, and a rail supply resistor to source. You do not want the gate voltage to put them full on, (you would then be up on the plateau), but say 50% on, then match for current draw. Texas explains in more detail, IIRC. I want to ensure he gets credit for this KEY piece of FET survival information that was "leaked..." :wink:

 

[rhitee05]

I would add a couple of minor points to bigmoose's advice.

Layout your board with both a single common gate resistor and individual resistors for each FET. As BM said, at least to start you can use just the common resistor and jumper the others. I'm a firm believer in planning ahead, especially with a prototype - put everything (or most) you think you might need on the board from the start, but only populate what you need. This lets you tweak later without breaking out the X-acto knife. You can cut out the un-necessary bits later when it's production time.

I'll go BM one better - instead of layout out 3 identical half-bridges, just design a board that's a single half-bridge and build 3 of them. Design the boards so they all connect to common battery and ground bus bars, otherwise the phases are independent of each other. This is less work for you and it also works well since it's basically the same price to buy 3 boards as 1 (most places require you to buy more than one anyhow), and each board is smaller. One board would hold 2 sets of FETs, caps, and a pair of current buffers.

One of the issues with current-sharing in linear arrays is making sure the current paths are identical. If the current path through one FET is longer than through another, that small bit of extra resistance will ensure that the current is never equal. The best way to do this is feed battery+ from one end of the array and ground at the other.

Finally, I'm not sure what the IR2110 drivers are for. If you're using an existing controller as the basis, it will already have all the level-shifting circuitry required to provide gate drive with appropriate voltages. All you need are the current buffers. Make sure that the layout provides a dedicated return path from the FET source (of each FET) back to the current buffer to keep this loop as tight as possible and independent of the high-current paths. You want to make this a "Kelvin"-type connection. You would need the IR2110's later if you wanted to drive this with logic-level inputs from a uP to make a completely custom controller, but that's not necessary for now.

 

[zombiess]

Ok i just sent a pm to etard askinf for a 3rd block and offered up money so well see if he goes for it. My orogonal plan was to build a modular setup but etard only wanted to do 2 blocks.

Im going to start redesigning the board(s) again for the 5th time now i think lol. Ill design one phase and price it, then all 3 phases together on one board and price it. Wont be much difference but i have to choose what i want to do and im trying to keep this smallish.

Bigmoose, is there any reason i have to use those tabbed caps u mention instead of just paralleling a few of the cheap 1uF low esr polys i have at each end? Do i really need a big 1000vac cap designed for a 500v igbt or can i get away with 275vac which is over 2x my working voltage as long as the esr is low? I beleive I measured the esr of the 1uF caps around 50 mOhm each. With 4 to 6 in parallel (half on each end of the rails) the esr is going to be pretty low. Low esr is why i chose polypropelene vs polyester or ceramic. Most snubbers are made from polypropelene like the big ones you pictured because of the low esr it has.

Rhitee05, i used the irf 2110s because of reading other info on driving several parallel fets. This driver setup with the buffer can slam the gates with up to 8 amps as drawn. I figured using it would eliminate any driver problems from the factory totem pole setup. It also draws very little power and i think i can parallel it off the on board 78L15or just add another one but need to double check my math.


R

 

[bigmoose]

Zomb, remember what I do... I can't say "sorta..." I also freely admit I am "ruined" for low cost, design and manufacture, I am locked into my life's paradigm. ... that said, I freely respect any design trades you guys need to make. Luke and Methods have shown me incredible progress by how they do things! I fully respect their approach to electronic design and manufacture, as I do yours. Remember, I pay $260 for a ceramic snubbing cap the size of a sugar cube,and it comes with a folder of paperwork certifying it.

I am doomed!

The caps I recommended are IMHO the lowest cost for ultra low ESR not considering an array of AVX ESCC caps. The tab gets the good internal ESR to the board. Do you need "the best", nope! You only need "good enough"... that you will have to determine by test and where you want to run your controller bridge. The need for "better" caps scales with max current and dI/dt. You can tailor the dI/dt to "get by" with whatever you put on the board, if you have the equipment to monitor during a run, and can "sneak up on it" from the safe side.

Oh and don't feel bad about the redesign. My rule of thumb is three turns after you have the brassboard working. To get that first prototype "sort of" running can be up to 7 or 8 turns... if it gets to 20, I encourage folks to find another field of work...

 

[zombiess]

Bigmoose, i have major respect for you and what you know and am very happy you joined in this thread to help me.

I love giant sexy low esr caps as much as the next geek but im trying to keep this small enough for a bicycle which has limited space so i must sacrifice somewhere for the sake of size and cost. I almost bought several of those spragues u mentioned when doing research for this project but the size really is a big detractor so i spent two days researching and learning about caps. I think with enough of what i have paralled at each end will be ok, but feel free to say i told u so if i smoke this.

Any additional thoughts on the buffer as mentioned by Rhitee05? Should i drop the irf2110 and just use the buffer stage driven by the on board drivers?

I have a 12 fet stage im trying out before building this so i will have an idea of how well my caps work without smoking lots of fets if it all goes wrong.

I forgot to mention that this is really not going to be pushed really hard. After reading all the info i have im amazed the xie chang controllers work so well. I modded my irfb4115 18 fet controller by pulling and sourcing power from the tabs. Ive peaked 101a battery which was around 260a phase and i regularly abuse it with 70a battery 170a phase for 10 mins almost non stop (session was over 100 wh per mile average for the ride )and use regen and do wheelies.
My highest recorded fet temp was 62c so far and that was due to excessive regen abuse.

 

[rhitee05]

The buffer stage is what's needed to drive the array of FETs. Because the buffer requires very little current to switch, it doesn't matter what drives it, even if it's the relatively slow Xie Chang drivers. To use the IR2110, you need logic-level input signals. That means you either need to hack into the board and use the logic-level signals before they enter the drivers or take the FET gate inputs and shift them back down (not desirable). And then the IR2110 is just duplicating the bootstrap and level-shifting functionality that already exists on the board. Might as well use it and just add a current buffer to drive the bigger FETs.

 

[hardym]

I may be readign the schematic wrong. The Low side FET gate drivers (from pin LO) have no supply voltage -- low side drivers should be driven from +15V.

The high side driver totem pole configuration is interesting. The high side gate driver voltage is powered from the IR2112, rather than an external charge pump or supply. So, I'm not sure what the totem pole is providing as the ir2110 can onlh provide 2A, the high side totem pole doesn't add any more drive current.

It looks like the totem pole configuration was lifted from http://www.irf.com/technical-info/appnotes/an-978.pdf figure 11.
Note that figure 11 schematic is only for low side driving where the top of the totem pole is driven from Vcc.

Mark

 

[bigmoose]

I forgot to mention that this is really not going to be pushed really hard.

This is a key piece of information, I think you'll be OK with this design perspective. When I saw water cooled, I assumed you were going to shoot for the moon. That said, see if you can place the caps you chose closer to the bank of FETs. There is a thread I posted on fixing a robot 3 phase controller with some leaded caps and changing the gate drive resistors to slow the FET switching down. The guys were blowing FET's and driver ICs. They have yet to blow a controller after the mods, (about 6 months of action so far) and have destroyed the gearbox by stalling the motor at low speed 3 days after the mod. The modified controller stayed together.

It's designed to be driven from either a DIY controller or an EB312 controller.

If your intent is DIY controller, keep the IR2110's. If you want to marry it to an EB312 controller, it will take some thought. Thinking about it for 5 minutes, I think I would keep a "new" gate drive in either case and snag the gate signals right off the micro pins on the EB312, and ignore the level shift, bootstrap, and timing resistors in the EB312. To do it you will have to reverse engineer their gate drive to snag the right 6 signals.

Keep at it, the joy is in the journey. Only you know what meets your design requirement. The rest of us are only suggesting with an incomplete picture. We wish you success with this!

 

[zombiess]

I may be readign the schematic wrong. The Low side FET gate drivers (from pin LO) have no supply voltage -- low side drivers should be driven from +15V.

The high side driver totem pole configuration is interesting. The high side gate driver voltage is powered from the IR2112, rather than an external charge pump or supply. So, I'm not sure what the totem pole is providing as the ir2110 can onlh provide 2A, the high side totem pole doesn't add any more drive current.

It looks like the totem pole configuration was lifted from http://www.irf.com/technical-info/appnotes/an-978.pdf figure 11.
Note that figure 11 schematic is only for low side driving where the top of the totem pole is driven from Vcc.

Mark

Good catch, I missed the VCC connection to +15V and the source pins of the low side FET totem pole. Fixed it now. It's a high/low driver lifted from figure 15 of that app note on page 17 That figure comes from International Rectifier Design Tips DT 92-2A.

I can use an separate 15V supply to feed the IR2110. Does this make more sense? I'm not going to pretend I fully understand it, I do my best to understand app notes and modify as necessary but I do a lot of cut and pasting then tweak to see if I get it to work right. Please also read my response below to bigmoose as it's also related to this.

If you want to marry it to an EB312 controller, it will take some thought. Thinking about it for 5 minutes, I think I would keep a "new" gate drive in either case and snag the gate signals right off the micro pins on the EB312, and ignore the level shift, bootstrap, and timing resistors in the EB312. To do it you will have to reverse engineer their gate drive to snag the right 6 signals.

Keep at it, the joy is in the journey. Only you know what meets your design requirement. The rest of us are only suggesting with an incomplete picture. We wish you success with this!

I figured I'd feed the IR2110 from the EB312. I also might graft it onto the EB312s 15V or 5V regulator or add a parallel one on my board. I'm not sure which way I'm going to go yet because the IRF2110 needs to the logic levels to be very close to VSS and VDD, but finding the gate drive signals from the GPM8F chip is pretty trivial. I also own several IRF2110s so it might be handy to have a few ready to go drivers for future experiments / projects.

I have a completely redesigned circuit and circuit board done I'll post up later tonight for critique, I appreciate everyone's help. Bigmoose, all the extra caps on the board can be considered your fault... it's also now capable of up to 36 TO-247 FETs...

Anyone have a link to a site that has a formula on how to estimate the gate resistor needed?

 

[bigmoose]

Anyone have a link to a site that has a formula on how to estimate the gate resistor needed?

Start with 10 ohms. Scope your transitions, adjust for 800nS to 1uS transition times. It is better to start too slow and trim up in speed because it limits dI/dt. When you lock in the number of FETs and type of FET I'll run it in my software and tell you where I would start with the gate resistor.

 

[zombiess]

OK, here is the newly revised 36 FET controller (up to 36 FETs). I went a little crazy with the caps, but it's not like all of them have to be used. Figured it's better to have too many options than not enough. I think I followed the advice correctly about putting the snubbers on each end. I put 3 in parallel + 3 from the ground circuit to the battery + rail bypassing the shunts.
The board measures about 9.75 wide by 7.25 high. and will have a constructed height of about 2 inches after adding all the copper to the traces and the water blocks.

This board does not contain the drivers, they will be on a separate board with twisted pair. I hope I setup the gates correctly for twisted pair. I wasn't sure if it's best to run a twisted pair to each gate/source from the driver (lots of wires) or to just do what I've done on this board and run a single twisted pair to the gate/source for each bank (6 twisted pairs). Someone let me know so I can wire it up correctly. If I need the lots of wires option I'll run the resistor on the gate driver board and then run the spaghetti of wires to the FETs.

I have a lot of questions because this is my first rodeo when it comes to designing something like this. Please critique away.

 

[bigmoose]

Zomb you work fast!! Yep, you likely have enough caps! I would place them where the orange circles are. Likely 2 of yours on each end are fully sufficient, and one is likely sufficient.

I also ran the gate drive calcuations. This is where I would start, and scope the transitions and adjust as necessary:

• Qty(2) IRFP4468 19 Ohm Singe Gate Resistor for the group
• Qty(4) IRFP4468 9.6 Singe Gate Resistor for the group
• Qty(6) IRFP4468 6.4 Singe Gate Resistor for the group

 

[mauimart]

I may have missed it but I did not see any provisions on the board for measuring phase current via a shunt or hall type current sensor. This seems the best way to prevent catastrophic FET explosions assuming the control side is designed to monitor and shut down the gates in time for an over current event.

 

[amberwolf]

Doing that would require altering the brains of the controller, too. AFAICS, this is basically just a power-stage to replace the FET section of a typical ebike controller with something a bit more predictable/reliable (since the brains seem to work well enough for basic work when power stages get beefed up).

I suppose it would be possible to add a bit of circuitry that monitors the phase currents on each phase, and concatenates those into a single output that equals the same response curve the battery current shunt measurement circuit has (on the original controller board), then analog-"OR" those two together into the MCU. Would require some modification of that part of the brain board, too, but all the necessary circuitry could be part of the power board(s), or could be a separate board if necessary.

 

[zombiess]

I may have missed it but I did not see any provisions on the board for measuring phase current via a shunt or hall type current sensor. This seems the best way to prevent catastrophic FET explosions assuming the control side is designed to monitor and shut down the gates in time for an over current event.

Provisions for 6 shunts are next to the ground input and will be tied to the eb312 and cycle analyst.

 

[zombiess]

Zomb you work fast!! Yep, you likely have enough caps! I would place them where the orange circles are. Likely 2 of yours on each end are fully sufficient, and one is likely sufficient.

I also ran the gate drive calcuations. This is where I would start, and scope the transitions and adjust as necessary:

• Qty(2) IRFP4468 19 Ohm Singe Gate Resistor for the group
• Qty(4) IRFP4468 9.6 Singe Gate Resistor for the group
• Qty(6) IRFP4468 6.4 Singe Gate Resistor for the group

I am using irfp4568 fets with a max voltage of 132v. I plan to stick to 125v as i run now. Could you run the resistor calcs for that and also explain the math or at least a link to the formula. I love to learn.

I wanted to place the caps there, but i have water fittings in the way and by the time i make room for them the path is just as long or longer so im trying to compensate by using wide traces which will have 10 or 12 gauge wire added to lower the resistance and inductance (it will lower inductance right?) . It one of those design compromises which must be made.
If this gets your seal of approval ill make a few more minor tweaks such as extra holes and then have 2 boards made up.

Fyi, the 1000uF caps on the main rail have about 200mOhm each and the 330uF caps are around 400 mOhm i believe. Is having this many caps ok or is it overkill and wasteful? I firured the less ripple the better and having 3 low esr snubbers in parallel at each end might help everything live better.

How long do you think i can go on the twisted pair gate (ill keep them as short as i can) feeds and do i only need one feed per phase? Thanks for your help. Im trying my best to learn and design correctly.

 

[bigmoose]

• Qty(2) IRFP4568 37 Ohm Singe Gate Resistor, 0.59Apeak required from driver, 3.27uF Min ByPassCap, 90mW drive Pwr
• Qty(4) IRFP4568 18 Ohm Singe Gate Resistor, 1.19Apeak required from driver, 6.29uF Min ByPassCap, 181mW drive Pwr
• Qty(6) IRFP4568 12 Ohm Singe Gate Resistor, 1.78Apeak required from driver, 9.31uF Min ByPassCap, 272mW drive Pwr

You should double or triple the minimum sizing on the bootstrap/driver bypass cap shown above. Also these are starting values. Build it, measure transition times, and trim the values, likely downwards. The results come from a mathematical driver model I have developed over the years for driving FETs/IGBTs in switch mode power supply/3Phase driver applications, it has basis in a number of industry data sheets.

Layout is always a compromise, you do what you need to do and measure the results. My "feeling" was that there was more than adequate electrolytics... perhaps 33% to 50% more than needed. You could populate 1/2 and measure.

One feed per 1/2 phase bank. You would have Qty (6) pairs going from your power board to driver board. You have the right thought, as short as possible.

Looks good. It is good to see more guys "rolling your own" controllers, drivers and power stages. This will advance the availability of this information, and lead to economic optimization of the designs.

Like any project, it may need tweaks, haywires and refinement once in hardware. Good luck!