OSHW TO247 IGBT watercooled laminated half-bridge

[marcos]

So, heres another motor controller. I was a bit involved in Vedder's VESC design, big fan of Benjamin's work, and I've been pushing to get some funds to develop this inverter. I'm aiming at 400V and around 400A battery amps peak.

So, main design inputs:
* x12 650V TO247 IGBTs per phase, 36 for the complete inverter
* texas instruments ISO5852S reinforced isolation IGBT driver with extra current buffer
* laminated bus, made from milled copper sheets. transistors leads welded to these sheets
* optional, but desirable watercooling
* open source, made in kicad+freecad, available in github.

Here is a preview, its still a work in progress, far from being ready to prototype.

Schematic: (CLICK ON THE IMAGE for the latest commit)



View attachment IGBT_board.pdf (probably old)





Here you can see the pcb layout better (click on the image)






Note the bus layers, from bottom->up they are VBUS-, VBUS+, PHASE, and pcb. The rationale behind this is that you get minimal inductance in vbus since both planes are very close, avoiding any current loop.
Film caps are placed in different directions:
(+ -)
(- +)
(+ -)
(- +)
So their internal current loops cancel each other. I got that from an app note http://www.mouser.com/pdfDocs/Cree-...or-Designing-with-Cree-SiC-Modules-part-2.pdf

When I say milled copper sheets, its because in the workshop we have a cnc and I think we can pull something like this

I never tried milling copper, I know its not that easy, but it shouldn't be impossible to cut a copper sheet. The cnc could also bend the copper 'leads', and even automate the spot welding process. Not that I'm keen to do that now.
Sheets can be separated with kapton or FR4. I kind of prefer FR4 because I can drill it precisely and it would help with the alignment of caps and transistors for welding, its critical to get everything solidly aligned to avoid bangs.

TO247 support is an aluminum heat spreader, 20mm thick. I drafted a 3D model of a simple milled watercooler that would fit the same way and provide a more even heat exchange and actual heatsinking. Not sure about how to press the TO247 against this heatsink.

About the schematic, its mostly based on a TI 22 kw eval board, with some extra thingies I learnt by reading and listening to smarter and more experienced folks.

The board is a simple 2 layer PCB, but when you count in the 3 copper sheets below it you can get a nice electromagnetic-wise design.

The brain would be a VESC board, I have experience in STM32 MCUs, Vedder's board has a 168MHz monster with fpu and ADC phase current sensing synced to the transistors PWM, CAN, RTOS, etc, and very open source.

So... I wonder how does this look to the inverter gurus? Is it an interesting approach to you guys?

I'm open to criticism and keen to learn, I could get some equations or guestimates very wrong and I won't notice until I start testing the actual thing.

 

[ecotech]

What do you mean what you say your company , you own it or work for it? And why do you make lithium titanate batteries? You don't like cobalt or phosphates?

 

[marcos]

What do you mean what you say your company , you own it or work for it? And why do you make lithium titanate batteries? You don't like cobalt or phosphates?

I own 25%, its a small company. I do like cobalt and phosphate, but we use our modules in iot and defense stuff because they charge fast and last long, its a niche market.

 

[ecotech]

Do you buy the chemical ready made or do you have furnaces and make the stuff yourselves? Wet method is troublesome.
Do you use carbonate solvent and hexafluorophosphate for the electrolyte ? Triflates are expensive. I haven't read much on titanates I discarded it because it has low energy density and all of lithium battery chemistry because of scarcity and cost.

 

[marcos]

We buy cells and make modules.
Please pm me if you like but dont divert the conversation from the inverter.

 

[Vanarian]

If you can cut down costs and maybe build a 150V 200A you'd walk straight into e-bike and e-scooter (big model) territory. Tha'd be huge plus.

there is also a big demand for 75V 300A VESC based controller! :wink:

 

[marcos]

If you can cut down costs and maybe build a 150V 200A you'd walk straight into e-bike and e-scooter (big model) territory. Tha'd be huge plus.
there is also a big demand for 75V 300A VESC based controller! :wink:

Not really interested in bike stuff, I want it to move a car, but if it fits in a bike and you're willing to build it, go for it!

I just updated a bit the design, the project is versioned in bitbucket.

Today I found a cool way to share kicad files, here you can see the layout
https://eyrie.io/board?id=e352bd20d9474dabb5ff85692d4ab1c1

That tool still doesn't like the schematic though.

I have to calculate an approximate gate resistor value, and check the gate resistors power rating is okay. I was worried that this driver doesn't support cycle-by-cycle 2 step turn off, it only does a soft turn off during a desat fault.
Is a separate turn OFF gate resistor enough to limit di/dt slew rate? I want to avoid the inductive spikes while switching off the igbt, not sure if a simple gate resistor will do the trick.

 

[marcos]

I want to put some safety built in regarding accidental shoot through in case both pwm inputs are high due to noise... or bugs.

Some approaches I see:

* differential signaling from the controller
* logic to avoid shoot throughs

Differential signals like RS422 or LVDS could make the transmission more reliable against EM noise, but I don't like having an extra wire/crimp/connection that can fail. I prefer having 3.3v signals twisted with a GND wire, so it will tolerate if one of the gnd connection breaks. This will decrease the max harness length, I wasn't planning on long cables tough. Also this won't protect against a firmware error.

Logic approach would be an IC monitoring both input signals, and forcing a fault or a mute in case both signals are high. The thing is.. a simple logic gate won't account for the deadtime required between driving the IGBTs, and I don't want to put an FPGA just to check deadtime... I'll think about this.

 

[marcos]

A simpler, maybe too simple approach would be this

It asserts a FAULT when a wiring or firmware failure makes both inputs high, which otherwise would trigger a kAmp shoot through that would have to be dealt with the desat protection.

Asserting the FAULT disables both IGBT drivers, and since I plan to connect all FAULT signals in the inverter together (3 half bridges, 6 FAULT signals), the whole inverter would be shut down until the MCU resets the drivers.
In this case, FAULT and inputs reach the driver IC at the same time, because there is another nand gate in the pwm inputs to negate them.

This won't deal with deadtime timings, its there just for crude failures. Deadtime between pwm is almost hardcoded in the microcontroller timer peripheral, its a one-time configuration during initialization.

 

[marcos]

One thing to note in this general assembly, is that the PCB is on top of a large copper sheet (PHASE) that swings wildly. These 2 parallel copper planes make a capacitor that couples PHASE with the controller GND.



This copper plate capacitor is 112pF between phase and gnd. Honestly I don't know how bad is that. I can shrink the coupling area with a smaller gnd plane, and with a smaller phase copper sheet. I can also send the phase copper to the bottom, so it becomes phase\VBUS-\VBUS+\pcb. This would have the same capacitor, but 'connected' to a potential that is not moving wildly as the phase line. This would make film cap leads longer increasing vbus inductance. I can also increase the separation between the pcb and the copper, but the IBGT leads will have to be longer and with higher gate inductance, and I don't like that.

Also changing the dielectric could lower that capacitance, using polymide instead of fr4, for example. It doesn't improve the situation that much, though.

Overall, I can get that parasitic capacitor down to ~20pF, but i don't know if thats still going to be a problem, high dV/dt in phase plane will be coupled to gnd, i don't know how much since there is no galvanic connection anywhere between controller gnd and HV

This could be another reason to go with differential PWM signals, but this particular problem should be addressed at the source of the noise, by decreasing this coupling.

 

[marcos]

Its down to 13pF, and it looks less harmful now.



Yellow would represent the phase coper sheet, green the pcb bottom gnd plane. They only overlap below the igbt driver ICs.

Its a 12mm x 14mm area on each side, 1mm separated from the copper sheet. That would be (12mm*14mm*2)*(4.7*8.854e-12)/1mm = 13.98pF and I can make the area smaller I if want to.

 

[zombiess]

I'd forgo that cap arrangement and use a single large DC link polypropylene cap right on the input for each phase. I used 600uF Cornell Dublier caps in my parallel research setups because the plan is to go > 1kA on low inductance motors. They can handle 100A RMS ripple current each and there are 3 of them. Cost isn't very low though at around $100each. Maybe just switch out those 16uF caps for some bigger ones like 60uF, the extra capacitance distributed over the DC bus greatly reduces turn off collector-emitter overshoot.

Any reason you don't want to use a working pulled module that you can pick up off ebay for a reasonable price?

Is that 450A desire peak or RMS? Continuous? Why use 2 gate resistors in parallel on each device vs 1 larger sized one?

Keep in mind that in a linear array there is a voltage divider and several inductors in series between each, you will start reach diminishing returns. The inductance can cause some interesting differences in current rise / fall times if it's high enough. Doubt that would be much of an issue for your layout, but the DC bus inductance also effects the overall current shape on each pulse with the closest devices to the DC link showing a high peak that falls until turn off and the furthest device taking time to ramp up to full current. In between the 1st and last device is a resistive divider which causes unequal current sharing. I placed 11 MOSFETs (22 per half bridge) in parallel that I hand matched for equal Vgs threshold voltage. Go big or go home, right?

Here is a pic of my test apparatus. If you follow the green loop you can see one of my Rogowski coils I used to make the current measurements in circuit without adding additional inductance of a shunt/sensor.


I've attached a page from my lab notes that shows this effect. Its proportional to DC bus inductance. My DC bus inductance was ~65nH
View attachment 1

I've been on break from doing parallel research for several months now, need to get back to it and share some more of my data after I summarize my notes into something more coherent. I managed to parallel 9 discrete devices with near perfect current sharing (mitigating all effects shown in my lab notes) and plan to scale it up to +25 devices.

 

[marcos]

I'd forgo that cap arrangement and use a single large DC link polypropylene cap right on the input for each phase. I used 600uF Cornell Dublier caps in my parallel research setups because the plan is to go > 1kA on low inductance motors. They can handle 100A RMS ripple current each and there are 3 of them. Cost isn't very low though at around $100each. Maybe just switch out those 16uF caps for some bigger ones like 60uF, the extra capacitance distributed over the DC bus greatly reduces turn off collector-emitter overshoot.

Well, I was aiming to an adequate capacitance and a very low inductance. I'm replicating Cree's setup that had less than 3nH of bus inductance. Higher capacitance caps are the same height, so in the same area i can go from 112 to 150uF at best. If I want to increase the capacitance I should put another row of these caps.

I thought that 112uF, 3nH, 98Arms per phase was a reasonable figure for 175A battery current, 437A sort of continuos phase current (I estimate phase I = 2.5x battery I). Thats a 70kw output, I don't really know how will it behave if I get 200kw through this for a few seconds.
There are examples out there about replacing something like 1500uf alum caps with smaller 500uF film caps for the whole inverter and getting much better performances. I'll check again to rembember and document this, you used a whole lot more uF's than I was accounting for.

Any reason you don't want to use a working pulled module that you can pick up off ebay for a reasonable price?

I wanted to go discrete so its upgradable at the igbt level. Also, in argentina there is no ebay, and we don't have much market for igbt modules, so not much to choose from.

Is that 450A desire peak or RMS? Continuous? Why use 2 gate resistors in parallel on each device vs 1 larger sized one?

I'm planning on 400v 70kw (sort of) continuous, and if this reaches 200kw peak for a few seconds it would be a good figure. Something I did wrong is that I don't have a motor yet, and I have to estimate some parameters.
I saw 2 parallel gate resistors per igbt in a tesla inverter, I guess those folks saved some area using that setup. I also happen to use a lot those 2512 smd resistors. I should move them a bit to decrease the current loop between top layer gate current input and bottom layer gate->emitter current output. https://eyrie.io/board?id=c5ac1a5f21ce4684914535b2669bd01a&active=layout&x=10418&y=97708&w=25212&h=17253&flipped=false&pours=true&layers=m10000008ae29100000000000000000000000000000000000000000000000000000000000000f1&sheet=0

Keep in mind that in a linear array there is a voltage divider and several inductors in series between each, you will start reach diminishing returns. The inductance can cause some interesting differences in current rise / fall times if it's high enough. Doubt that would be much of an issue for your layout, but the DC bus inductance also effects the overall current shape on each pulse with the closest devices to the DC link showing a high peak that falls until turn off and the furthest device taking time to ramp up to full current. In between the 1st and last device is a resistive divider which causes unequal current sharing. I placed 11 MOSFETs (22 per half bridge) in parallel that I hand matched for equal Vgs threshold voltage. Go big or go home, right?

I've attached a page from my lab notes that shows this effect. Its proportional to DC bus inductance. My DC bus inductance was ~65nH
View attachment 1

The distributed cap setup has a good current sharing in the bus side. The phase output is not that good, the transistor closer to the wire will see less resistance than the farther one. Cool to see your testbench, thanks, I should do that.
I wonder which mosfets did you use, I'm selecting IGBTs that are designed to provide a healthy current sharing with positive Vce(ON) temp coefficient. In general IGBTs are more forgiving for current sharing, given that you chose the right one and put it in the right place. Well, tempco helps at the overall power output, C, ESL and ESR kills in the quick transients.

I've been on break from doing parallel research for several months now, need to get back to it and share some more of my data after I summarize my notes into something more coherent. I managed to parallel 9 discrete devices with near perfect current sharing (mitigating all effects shown in my lab notes) and plan to scale it up to +25 devices.

That sounds like a lot of current. A lot.

 

[zombiess]

I take back what I said about getting rid of the distributed caps, but I would most likely increase the capacitance by adding a +100uF cap directly to the input pads. I was looking for my notes when I experimented with DC link cap location but I must not have made them. I experimented with up to 3 additional 1uF to 30uF caps placed across the DC bus at varying intervals in addition to the big DC link cap at the input terminals. On another design I came up with from what I learned on this one, I found that having lots of distributed cap was not enough to kill resonance excited in the bus after the initial turn off overshoot. When I added a 600uF cap in addition to the three 30uF caps all resonance was eliminated.
What I found was having lots of cap reduced the resonant frequency + amplitude (and therefore it's energy) of D-S voltage swings after the initial turn off spike, at least in my case. I also added a single gate-source cap that I used to tune out turn off overshoot to allow faster switch times an gain voltage margin from less overshoot. I've posted scope shots of this in previous build threads. I haven't found any other publications that use as high of a G-S cap as I have or similar results to what I've experienced so take it for what it is, but having it as a DNP part isn't a big deal.

It's can be difficult to get a feel for a lot of this until it's on the bench and you actually get to scope it to see what's going on unless you've already built a similar design. Have you built previous inverters/drives? Most of my stuff that has spun a motor in real life only been medium power so far 10-18kW peaks on 100-125V DC bus with one design being capable of 7.5kW continuous on 115V bus.

 

[marcos]

Thanks, thanks.
The suggestion of an extra >100uF cap in the input is a good one, I'll check how to make room for it.

I have one G-S cap placed for all transistors at the gate driver circuit:
https://eyrie.io/board?active=schematic&id=c5ac1a5f21ce4684914535b2669bd01a&sheet=1&x=7753912&y=2936624&w=515801&h=661945&flipped=false
I can also tune the gate on and gate off current with different resistors.

One big difference between your setup and mine, is that mosfets have a very sharp turn off, and thus very scary overshoots. IGBTs on the other hand, have slower turn off times and less overshoot. Even driving hard the gate to -8v i dont think I'll reach your turn off speed.
Anyway, its all about managing these transients, so I'll focus on this.

I dont have much experience, only built one mosfet inverter, around 3kw peak, so this is a big leap in power for me.

 

[HighHopes]

i didn't read your thread in enough detail to give you any feedback, i'm too busy at the moment. but i did see that zombiess is giving you advice and i KNOW he knows what he's talking about so you're in good hands. follow his advice, ask questions so you understand. he can explain it all, and probably explain it better than i can too :wink:

 

[Njay]

What PWM frequency are you planning on using, Marcos?

 

[marcos]

What PWM frequency are you planning on using, Marcos?

20khz at most. I'll probably use lower than 10khz

 

[Njay]

You want to stay away from the resonance frequency of the battery - controller(power input caps) parasitic inductance with the controller's power input caps.

 

[marcos]

You want to stay away from the resonance frequency of the battery - controller(power input caps) parasitic inductance with the controller's power input caps.

Thanks Njay, good to know. If cree's app note is right about the caps layout these half bridges should have <4nH and ~120uF, the resonance freq should be very high.

Let me know if you see anything odd.

 

[Njay]

It's not the bridge's layout stray inductance, is the one from the battery - controller (the caps) loop (mainly wiring; depends on how long and far apart are the battery cables and such).

 

[marcos]

Oh, okay okay, I'll keep that in mind. Battery pack is not laid out yet.

 

[zombiess]

Oh, okay okay, I'll keep that in mind. Battery pack is not laid out yet.

To avoid what Njay is referencing (great point Njay!) you must keep the batt to controller leads as short as possible (reduces stray L) minimize their loop area. Inductance + loop area = the enemy, at least from battery to controller and DC bus to power devices. I actually found having a little higher inductance on the device leads (a few extra nH) can be beneficial to a point as it can lower the magnitude of the turn off overshoot by slowing it down (I did not expect this, but it makes sense). I no longer focus on keeping the TO-247 device leads super short as I have in the past. It's a balancing act as too much lead inductance and too much distance between the first and last device + higher lead inductance will cause a delay in the current rise. Device closest to DC link will have a faster current rise than the last device due to DC bus stray L + device leg stray L. I've seen the delta as high as 100ns when the distance from the first to last device was ~200mm with 30nH DC bus inductance between the devices. Your bus should be much less than mine due to it's increased surface area. I think my lead inductance was around 3nH-5nH per device.

What material are you using as a dielectric between the pos and neg bus and how thick will it be?

 

[Njay]

When polypropylene caps are involved, it means much lower total capacitance at the power input than with electrolytics, and we may accidentally hit resonance territory (you don't need to be spot on to be affected!). Controllers in this power range made with electrolytics need to have lots of them because of ESR, going in the thousands of uF, so resonance is not a problem for the typical PWM frequencies; see the table for high values of capacitance (I've never measured a battery - controller loop inductance but it's surely not below 100nH, probably even not 200nH in a bicycle/bike/car - a simple guesstimate at 10nH/cm).

I agree with you Zombiess that a little inductance may be beneficial, but not on all leads. For example the node top-FET-src / bot-FET-drn / motor-lead (if using all N-FETs) should have as little inductance as possible between the FETs, because the motor current will commute between the top/bottom FETs (no problem with inductance on the path going to the motor).
I'm mostly certain that my small H-Bridge layout was saved by having "quite a bit" of bottom FET source inductance (from DC link caps / FET driver to the FET's source). This inductance is a negative feedback on the charge/discharge of the gate, limiting the rate of drain current change; the higher the FET source current the higher the voltage drop at that inductance and the less capable the driver is to charge/discharge FET's g-s (stray inductance voltage subtracts from driver voltage). I'm yet to explore using this to equalize paralleled FETs current change rate (introduce, by layout, a fixed known inductance at the bottom FET's source leg). Still switch start sync is needed.

Also think it's hard to equalize inductance from power input to FETs. I see it only being done with a circle layout (although still some differences may exist unless you have only 1 cap with a tube-in-tube or rod-in-tube connection to the PCB) or distributed capacitance with a tree-like power delivery.

Another approach I still have to investigate is to not worry about distance from the the bulk capacitance to the FETs (as close as possible but no worries about that) and then let distributed high quality small caps "on" the FETs deal with the stray inductance from the bulk capacitance to the FETs. Anyways, I digress

 

[bigmoose]

A while back when working on a water cooling system for TO 247 FETs I was looking at a 1/4 inch to 3/8 inch thick by 1 inch or so wide trip of aluminum furnace brazed to a 1/4 inch or 3/8 inch water/antifreeze tube tube. I like to add one drop of surfactant to the coolant (think Dawn dishsoap). Just an idea to consider if it meets your heat transfer requirements.