bigmoose
1 MW
I would bet the measurements you have already made with your ohm meter are sufficient. Sometimes with the external circuitry, and the internal design of your meter, you can get false positives for a short. But since you did all three phases and two phases tested OK, one phase tested bad, chances are that you have the shorted FETs identified.
As to the other questions. The FETs used are Nchannel devices. Think of them as a simple switch. The Drain goes to the more positive voltage, and the Source to the more negative. Think of the Gate is the lever that turns on the switch. When the Gate goes about 4 volts above the Source the FET is fully turned on. It has a resistance though which is Rds On in the data sheets. If the Gate goes either 20 volts above or below the Source it can fail by the oxide "punching through." The Gate is very, very thinly insulated from the Source to make the device work. If the insulation were thicker, it would be insensitive. The Fet can also fail by punch through if the Drain gets appreciably above the Source voltage rating. These voltage excursions are typically the ones that kill our controllers. They are controlled, not eliminated, by the capacitors we place across the bus. When we stress controllers, it is my opinion, that the bus capacitors are more important than the FETs to the controllers survival.
In your controller there are Two FETs paralleled in what we call the "Top" FETs of the H-Bridge, and two FETs paralleled in the "bottom" FETs position of the H-Bridge. This is done to increase the current capability of the controller. When FETs were first developed, the TO-220 package was more robust than the silicon die itself. As time progressed and silicon processing and doping progressed the die got stronger than the package itself. For example there are only two 0.015 inch aluminum wires going from the Source tab to the Source pad on the die. All our power has to go through these short, but very thin wires. The capability of these "bond wires" or "bond out wires" is what gives the "package limitation" on amperage. The intrinsic capability of the silicon is called the "silicon limitation" on amperage in the spec sheet. Typical installations will be thermally constrained at a current below these two "theoretical maximum" values. Typically 40% to 60% of them.
This might help on explaining 3 phase and how the FET H bridge is configured:
http://ebldc.com/?p=147
As to the other questions. The FETs used are Nchannel devices. Think of them as a simple switch. The Drain goes to the more positive voltage, and the Source to the more negative. Think of the Gate is the lever that turns on the switch. When the Gate goes about 4 volts above the Source the FET is fully turned on. It has a resistance though which is Rds On in the data sheets. If the Gate goes either 20 volts above or below the Source it can fail by the oxide "punching through." The Gate is very, very thinly insulated from the Source to make the device work. If the insulation were thicker, it would be insensitive. The Fet can also fail by punch through if the Drain gets appreciably above the Source voltage rating. These voltage excursions are typically the ones that kill our controllers. They are controlled, not eliminated, by the capacitors we place across the bus. When we stress controllers, it is my opinion, that the bus capacitors are more important than the FETs to the controllers survival.
In your controller there are Two FETs paralleled in what we call the "Top" FETs of the H-Bridge, and two FETs paralleled in the "bottom" FETs position of the H-Bridge. This is done to increase the current capability of the controller. When FETs were first developed, the TO-220 package was more robust than the silicon die itself. As time progressed and silicon processing and doping progressed the die got stronger than the package itself. For example there are only two 0.015 inch aluminum wires going from the Source tab to the Source pad on the die. All our power has to go through these short, but very thin wires. The capability of these "bond wires" or "bond out wires" is what gives the "package limitation" on amperage. The intrinsic capability of the silicon is called the "silicon limitation" on amperage in the spec sheet. Typical installations will be thermally constrained at a current below these two "theoretical maximum" values. Typically 40% to 60% of them.
This might help on explaining 3 phase and how the FET H bridge is configured:
http://ebldc.com/?p=147
200 - 300 ohms works fine for me.
