rhitee05
10 kW
Pat,
It's always nice to have someone else look over the math. I'm not sure if this was my primary source during that previous discussion, but Fairchild Semi has a nice app note on making these calculations:
http://www.fairchildsemi.com/an/AN/AN-6005.pdf
Since we're discussing cooling, we need to make sure we break down exactly how the losses are distributed across the various FETs. I think that you can assume that commutation is happening much more quickly than temps are changing, so the high-side losses are averaged across the 3 banks and the low-side are distributed across the 3 banks. I expect that means the low-side will end up hotter, but the calculations will tell. The limit of the system will be determined by the hottest bank, so it's not accurate to take the total loss and assume it's evenly spread across all FETs.
If you want to be really particular, you could see what happens in the worst-case which would be operating at zero speed - so no commutation changes. In that case one of the high-side banks would see all the high-side loss (3x the average power). On the low side, one bank would see all the diode loss and a different bank would see the conduction loss, so worst-case would be the higher of those two (almost certainly the diode loss). If you can make the cooling effective enough to handle these loads, then you should be fairly well-protected against popping a FET. At least, due to thermal stress. :-D
It's always nice to have someone else look over the math. I'm not sure if this was my primary source during that previous discussion, but Fairchild Semi has a nice app note on making these calculations:
http://www.fairchildsemi.com/an/AN/AN-6005.pdf
Since we're discussing cooling, we need to make sure we break down exactly how the losses are distributed across the various FETs. I think that you can assume that commutation is happening much more quickly than temps are changing, so the high-side losses are averaged across the 3 banks and the low-side are distributed across the 3 banks. I expect that means the low-side will end up hotter, but the calculations will tell. The limit of the system will be determined by the hottest bank, so it's not accurate to take the total loss and assume it's evenly spread across all FETs.
If you want to be really particular, you could see what happens in the worst-case which would be operating at zero speed - so no commutation changes. In that case one of the high-side banks would see all the high-side loss (3x the average power). On the low side, one bank would see all the diode loss and a different bank would see the conduction loss, so worst-case would be the higher of those two (almost certainly the diode loss). If you can make the cooling effective enough to handle these loads, then you should be fairly well-protected against popping a FET. At least, due to thermal stress. :-D