Ebike Battery Monitoring and Control System

Here is what I got from an apps engineer at Intersil in response to a few questions. Answer 1 is encouraging.

1. The ISL94208 was just released, so it should have at least 10 years product life.
2. The TEMP3V, CFET, and DFET pins can be left unconnected. ISREF, CSENSE, DSENSE, VMON, and TEMPI should be connected to VSS if not used. Connect WKUP to VBACK if not used.
3. VFET1 and VFET2 are only used for power FETs, so they are not needed. They might be left unconnected, but we have not done a lot of testing with the device in that condition. I would connect them to CELL2 and CELL3 as shown in the diagram.
 
2moto said:
Here is what I got from an apps engineer at Intersil in response to a few questions. Answer 1 is encouraging.

1. The ISL94208 was just released, so it should have at least 10 years product life.
2. The TEMP3V, CFET, and DFET pins can be left unconnected. ISREF, CSENSE, DSENSE, VMON, and TEMPI should be connected to VSS if not used. Connect WKUP to VBACK if not used.
3. VFET1 and VFET2 are only used for power FETs, so they are not needed. They might be left unconnected, but we have not done a lot of testing with the device in that condition. I would connect them to CELL2 and CELL3 as shown in the diagram.
Click to expand...

Excellent!

I like that Intersil also sells parts at small quantity directly, their price is even reasonable (not sure about shipping costs). It makes it more plausible that they will be available to small quantity users.

Good data on setting up stuff for non-use, I was thinking very similarly, good to have some apps engineer suggestions.

This is looking better all the time.

If we use the 3.3V regulator capability of the Intersil chip (with external NPN) to power the micro there will be some issues on starting it when charging and discharging. This appears to be covered in the data sheet, but I haven't looked carefully enough to see if there are interesting issues there. I think I want this unit to power up when there are serial comms from the master node, but if the micro is powered off the interrupts won't work. I think the regulator and chip power off together, not sure if we can leave the regulator on but power the rest of the chip down, and what the regulator minimum idle current draw is. The micro I'm looking at has 0.1uA power down state, so would like to not add too much to that. Might not be all that worthwhile powering the chip down if it is configured right the power may be low enough. Lots of details to look at.
 
Alan B said:
Teh Stork said:
Came to think about it; regarding your concerns with SPI/serial comm. Implement a checksum algorithm. This drastically increase EMI, but errors in transmission are easily dealt with.
Click to expand...

Thanks for the comment.

Definitely in the plan. :D
Click to expand...

Good :)

Just want to clarify this sentence, it can be understood several ways if you're new: "This drastically increase EMI, but errors in transmission are easily dealt with." Clarification: "This drastically increase ElectroMagnetic Immunity so errors in transmission are easily dealt with". Think I made a bummer with the EMI-reference there. (Norwegian EMC lingo differs somewhat from english)...
 
Has anyone taken apart one of those Cell Log devices? They are cheap, fairly accurate and would seem to be a good analog front-end for a BMS. How do they solve the level shifting? As it has an LCD display it presumably uses a microcontroller, but what's in front of it? Anyone know?
 
Yes, there are schematics on the web somewhere. It is an AVR and some op amps as I recall. It draws different amounts of current from each cell, enough to imbalance a pack if left on there. The AVR also powers itself from a cell as I recall, and the op amps power from different cells.

Here is some discussion about it on ES:

http://endless-sphere.com/forums/viewtopic.php?f=14&t=20142
 
Learning the Intersil ISL92408 4 to 6-Cell Li-Ion Battery Management Front End

Sales Page:
https://www.intersil.com/en/products/power-management/battery-management/cell-balancing-and-safety/ISL94208.html

Data Sheet:
http://www.intersil.com/content/dam/Intersil/documents/fn83/fn8306.pdf

The usual procedure is to read the datasheet a few times and understand each function and each pin. Make a list of issues that need attention.

Issues
Need to put chip to sleep to get low power mode (<10uA)
When asleep the 3.3V regulator feature shuts down, this removes power from the separate micro if it powers from there
Need to wake up on charging and discharging, micro will power up each time
Backup power provided by Vback pin, recommends 2-4.6V all the time, often powered by Cell 1 (<3uA)
The Wakeup pin can be programmed for low or high going wakeup
Watch the voltage levels on the wakeup pin, it can cause higher current, pullup to Vback for low going wakeup
The mux routes the cell voltage to an output pin after offset and scaling providing a 0-2.15V ADC signal
The mux needs to be deselected from all cells to minimize cell leakage current
The accuracy of this mux'ed cell voltage probably needs calibration (and the micro does also)
It takes 0.1mS for the analog output to stabilize to 1 part in 200 (wait longer for 10 bit accuracy)
Probably won't use features related to charge/discharge control FETs, handle those separately
Make sure to terminate the unused pins appropriately, also VFET1,2 supplies
SDA and SCL may need external pullups (i2C serial)
Wiring for 5 cell configuration skips cell 2 and makes other changes, beware
How much dissipation in the chip due to balancing currents? 10 ohms, 400mW max cont total dissip, i = sqrt(.2/10) = 140mA total for all 6 outputs??
Further documentation in the evaluation kit would be useful to review

That's all for now
 
That's a pretty good list. While I've adapted the schematics and completed layout of my existing design to use this chip, I won't get much beyond that in the next 2-3 monts due to lack of time. That is, I won't actually build PCBs or rewrite the micro code. I *might* be able to sneak some time to do a bread board test without the micro interface.

I hope you are able to make progress and I'll follow this thread with interest.
 
We'll have to see how it goes. I've got a partial PCB layout and a mostly schematic, but need to move both into a better ECAD package that I need to relearn. Other projects may take me away from this for awhile as well.

I worked out a way to wakeup the chip from the serial. Since the micro is powered down a separate hardware path was required. It would be nice to avoid the extra hardware.
 
I just use a very low ground pin current voltage reg (< 4uA typ.) to keep the micro powered in sleep mode from which it wakes periodically. It then wakes the Intersil chip, measures the voltages, temp, etc., transmits results back to master and goes back to sleep. When charging, it's always awake.

For ECAD, I'd recommend Eagle CAD. When combined with a plug-in called Eagle-UP, you can get a very good Google Sketchup model, which has been a great help in the mechanical design of various projects (see attachment as an example).
 
Very nice board rendering!

Eagle is very popular. Unfortunately it has a big learning curve and I've never used it. There's also KiCad and DipTrace.

Good on the low quiescent current regulator and keeping the micro asleep. That is a good way to go. For me it is boiling down to a trade between doing that (I've done that in a flashlight regulator I built), and getting the serial to wake the Intersil chip and have it power the micro. I think we still need to put the regulating transistor on the Intersil chip so it can make 3.3V for itself, even if not used by the micro. So the 3.3V is "for free" taking no parts. Perhaps 3.3V can be brought in externally from the other regulator and skip the external NPN, I have not looked into that. Not sure what the sleep power would be in that case, or whether it is even allowed.

At the moment I'm following the design idea where the separate master board is on during charge and discharge, and it wakes the nodes with the serial line, sending a pulse long enough to meet the Intersil chip's wakeup requirements, and each one passing that along to the next in the chain. Once awake they stay awake and respond to commands until they either get a sleep command or time out on lack of commands and go back to sleep on the Intersil chip which powers the micro clear off.
 
A little progress to report. Have the basic layout up in the new layout software package. I've used this software on a couple of projects before. I particularly like the (to me) straightforward learning curve, I have a lot of experience with ExpressPCB, and this program is similar but much more sophisticated and not tied to one PCB vendor. I have not had to read the manual. Their library has the QFN parts so I have not had to make any library pad layouts (though this program has one of the better pad layout tools). I'll have to check them to make sure the dimensions are correct, but it looks like all the parts I need are in there. It has been awhile since I used this program, but it seems to be coming back very quickly.

I'm doing it somewhat backwards, laying out the board and doing the schematic after, but it is more interesting that way and the part numbers fit the physical layout better, and I have a schematic in the other package to follow anyway. I will have to make parts for the schematic on the Intersil chip, I suspect.

If you are happy with your current PCB layout software, skip the next paragraph.

For folks looking to learn a PCB layout program that doesn't tie you to one (expensive) vendor, DipTrace is worth a look. For me it was easier to learn than the frustration of Eagle or KiCad, and it comes in various varieties from free and nonprofit to full professional / commercial. The free version will do 300 pins, autorouting, no board size limit, two signal layers and as many ground/Vcc layers as you want. The library has a lot of good stuff in it, and you can make your own pad layouts easily with the graphical pad editor. I've tried quite a few free/inexpensive PCB layout programs and DipTrace has been the best for me so far. (I get nothing from DipTrace, other than using their free version, and I will almost certainly end up buying their package soon). I like that you can upgrade between their packages by paying the difference, great for small projects and small businesses that there is no penalty for growing within their product line.

For PC boards I'm going to use OSH Park. I've tried a few others but for small runs and prototypes I've heard (from a variety of sources) that OSH Park is a great choice (ES Methods has used them also). Three double sided boards for $5 per square inch, including shipping.

For this board the area will be about 4 square inches, maybe a bit less. So $20 for three prototype boards, and about $4 each for a small production run of 40 boards from the same source (if it comes to that).

Here's a tutorial on setting up DipTrace for OSH Park board production - http://cryoarchive.net/tutorials/diptrace-tutorials/diptrace-design-your-pcb-for-oshpark-com/

I discovered that DipTrace will support rotating components other angles such as 45 degrees. This facilitates connections on the small square QFN packages. This is a feature not all packages support, and it is very helpful.
 
I ordered a test pc board from OSH Park tonite. This is a different board from another project that I needed a few more of, so I'm using it as a test of the process as well.

I used the default DipTrace names for the layers and "gbr" extension, plus an Excellon file, all mashed into a zipfile named after the board and revision. This seemed to work right off and was much less work than renaming them to Eagle style filenames.

Cost for this 4.5 by 1.25 inch board was about $28 for three boards, not bad at all for a board with solder mask, top and bottom silkscreen plus gold plating. :)

Now we wait on that while we work on the battery data acquisition board. On that one we continue to work through getting the parts and traces on and organized.
 
That OSH Park supply sounds very good. I usually use a more local (to me) supplier which charges 55 Euros for about the same board space. I'll have to check if they do international shipping and whether that's still economical. At the cost of OSH Park, it not even worth bread boarding anymore.
 
I believe OSH Park does international first class postage for $5, which sounds very good. Not sure how long that takes to get there. It is probably slower than local, local turnaround here is often less than a week, but it does cost more.

I agree for many things it is not worth breadboarding, unless they are very simple or very risky.

The battery interface board is progressing. Moved some parts around to reduce vias. Need to do a schematic though, it is getting a bit complicated for going straight to layout. Still have the regulator and wakeup circuits to add.

Need to make another board for calibration and testing. Something that plugs into the DB9 and allows me to connect an accurate meter to measure cell voltages. I'm thinking that I'll use a 6S Lipo charged to about 4.15 to calibrate with. Make accurate measurements of the cells with a good meter while the micro is also measuring and averaging the same cells. Feed both sets of readings into a calibration file for that board. Then when I compile software for a board I'll select the cal file that goes with it and the calibration factors will be precalculated right into the code. Could put them into eeprom instead of course. We'll decide that later. But in either case need to get the data. That will calibrate the ADC in the Micro, as well as the Intersil chip. We should be able to get below 10mV accuracy with some averaging, at least at normal temperature.

Another board I've made in the past has a CellPro wired to a DB9 for anytime verification. So if the system is not working, or just suspect, you can plug into the DB9 and check it out. Another of the same boards can be used to connect to an external balancing charger if that is needed, say to measure battery capacity, or balance things to the millivolt. One small board design can be used for all these purposes if it has a couple sets of pads for wires/connectors/meter probes etc.
 
What I did for calibration of the internal Vref was:

1) Store the values in EEPROM; a command can set them/read them from the system console.
2) Have a "raw ADC read".
3) The calibration is done with the system running but the cell monitor plugged into controlled power supply with enough voltage set precision.
4) Then a calibration step can be performed with a command from the console, which consists basically in a message to the user saying "set 2.500V and press OK", then the user sets it and presses OK, then "set 3.800V and press OK", then the user sets and presses OK and it's done, another cmd will store the calibration to EEPROM of the cell.

For the calibration I use a table of "base" and "slope" per "channel", which maps the ADC count directly into the final quantity.

I haven't explore much the calibration procedure possibilities, but this one, allowing to calibrate anytime with relative ease, seemed to me the simplest, at least during development. With more code space I'm tempted to write a bootloader capable of re-burning the code on the cell monitors, but having worked professionally on this kind of system, on some aspects makes me cringe to think about the problems that may arise; I'm already not very comfortable with code to write the EEPROM on the chip. I would rather have the calibration be stored at the console, having a unique number assigned to each cell monitor or knowing the ring position of each; then even the cell monitor code would be simplified, moving complexity into the console, which is a bigger and more upgradable system.
 
Not sure what you mean exactly by that drift, but I don't expect any relevant drift. The internal Vref shouldn't drift more than a very few mV over temperature and there's only 2 resistors (resistor divider) in the measuring path.
This way of doing calibration does, of course, accommodate the resistor's tolerance which is a nice advantage; I'm using super normal 5% tolerance resistors. I'm measuring with nominal resolution of 5.1mV; "nominal" because of Vref and resistor tolerances. 1.1V Vref on these AVRs has an initial tolerance of about 9%, all of this must be taken into consideration as to be sure that the desired measuring range is achieved.
 
You should check out the link in my signature, I'm doing almost the same thing you are just with the tiny84 instead of 25/45/85. I've built up a prototype and it's working quite well.

Regarding measuring the cell voltage with the internal bandgap as a reference, don't bother. I tried it and while you can calibrate the internal reference just fine, the first 10 or so measurements are junk. I suspect it's too high impedance to charge up the sample and hold cap for the ADC fast enough, so the measurements approach what the actual value is in what looks exactly like the curve of a cap charging up. Yes, drift is low, but if you're concerned at all about power consumption you'll shut the ADC down between measurements, and once you start it back up you'll find it takes 10-20 measurements to stabilize again.

I used an external reference as the input to the ADC mux, and the cell Vcc itself as the reference input. After that the math is simple to convert ADC counts into cell voltage. Actual accuracy turns out to be around 2 counts or so, just like you predicted.

I have a few other comments on your schematic, I'll reply later today, have to head out now.
 
I don't see any problem with the 1st readings, I do average of 2 readings, and I turn off the ADC between measurements. I took care with 4 things:

1) I only use the internal Vref and never switch between Vrefs (like internal and Vcc). And no AREF pin capacitor.
2) The resistor divider provides less than 10K output impedance and there's a 100nF cap to help hold the measurement voltage stable.
3) I keep internal Vref selected all the time.
4) Do the reading in sleep mode.

I'm running the ADC clock at 125KHz and system clock is 4MHz (RC).

If you have a cap at the AREF pin, this can take time to charge since the output impedance of the Vref is around 32K, although I think this should happen only at power up, but who knows, due to low power requirements and all.

I do see a potential problem with enabling/disabling the resistor divider, which I have not yet implemented. The filtering cap may take time to charge, I'll have to try it out and do some calcs to see with what margin it's running.
 
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