fet suppliers

[bobmcree]

Have you idea what are you doing when you replacing fets ?

I have successfully replaced the fets in many controllers which people are happily using. how many have you replaced?

when looking at the miller charge you are considering how fast the fet could be switched if there was adequate drive current. you are not necessarily able to determine the suitability of one fet to replace another in an existing design.

when i posted that the mj10016 was fast enough, i was referring to the gradient coil power supplies we used them in on some of the first mri machines which i helped build. i did not mean to suggest that they could be efficiently used in a modern switching power supply running at 100 kHz. i apologize for any confusion that comment might have created.

if you have something positive to contribute, i know all here would welcome it; if you want to find something to attack in my posts i am sure you can find it

 

[bobmcree]

eP's comments caused me to go back into one of the textbooks i put on the shelf and re-read some fet theory i had stored away in the dark recesses of my old brain. i expected that because the fets were all IR products in the same general family that the miller charge would be similar, and that the gate capacitance would make a bigger difference. i was wrong.

indeed, as the data he posted shows, the Miller value is higher for the 4310 than it is for the stock 4710 and for the 4110. the values for the 4710 and 4110 are within 10% of each other, while the 4310 is 50% higher.

what this means is that the 4110 is actually a BETTER choice for replacing the stock 4710 than is the 4310. the 4310 will require more current to charge the gate than either the 4710 or the 4110.

i have replaced the fets in a 20a controller with the 4310, and it worked fine. this is an indication that the 4110 would work even better. i have a 20a unit i need to repair, and i will stick in a set of 4110s and expect it should work fine.

i have said before there are lots of things i don't know, or in this case that i have forgotten. thanks to eP for setting things straight.

 

[Lowell]

The 4110's work very well as an upgrade, and Justin's scope verified that everything happens as it's supposed to.

 

[eP]

indeed, as the data he posted shows, the Miller value is higher for the 4310 than it is for the stock 4710 and for the 4110. the values for the 4710 and 4110 are within 10% of each other, while the 4310 is 50% higher.

what this means is that the 4110 is actually a BETTER choice for replacing the stock 4710 than is the 4310. the 4310 will require more current to charge the gate than either the 4710 or the 4110.

Thanks Bob for info.
Now i feel almost as a senior FET advisor :lol:

BTW i hope my previous questions wasn't received by Dan as too offensive and he come back to the forum activity soon.

 

[fechter]

The 4110's work very well as an upgrade, and Justin's scope verified that everything happens as it's supposed to.

Cool. I like actual test results.
With 4110's in the 20 amp controller, it should be possible to bump up the current limit a bit, like around 30 amps or so.

 

[The7]

indeed, as the data he posted shows, the Miller value is higher for the 4310 than it is for the stock 4710 and for the 4110. the values for the 4710 and 4110 are within 10% of each other, while the 4310 is 50% higher.

what this means is that the 4110 is actually a BETTER choice for replacing the stock 4710 than is the 4310. the 4310 will require more current to charge the gate than either the 4710 or the 4110.

Thanks Bob for info.
Now i feel almost as a senior FET advisor :lol:

BTW i hope my previous questions wasn't received by Dan as too offensive and he come back to the forum activity soon.

Thanks for to draw us to the attention of Miller charge and the rise and fall times of the FETs.

For 4110: rise time + fall time = 67+88 = 155ns=0.155ms
Rdc(ON) = 3.7m ohm

For 4310 rise time + fall time = 110+78 =188ns=0.188ms
Rdc(ON) = 5.6m ohm

Assume current = 75A, voltage = 65V;
PWM period = 1/17kHz = 58.8ms

For 4110:
Switching loss due to "rise time + fall time" = 65*75* (0.155m/58.8m)/2
= 6.4 W
Rdc(ON) loss = 75*75* 3.7m= 20.8W

For 4310:
Switching loss due to "rise time + fall time" = 65*75* (0.188m/58.8m)/2
= 7.9 W
Rdc(ON) loss = 75*75* 5.6m= 31.5W


The switching loss due to "rise time + fall time" for 4110 is less by 18%
The Rdc(ON) loss for 4110 is less by 36%.

For the ebike application, the Rdc(ON) seems to be the more important parameter for the controller heating and loss.

 

[giveahoot]

So then basically there are costs between the two variables on-state resistance vs. voltage. And the 4310 would also have to withstand more voltage in the off-state, and thus generate more heat with less volts, except at full load? Therefore, it's not necessarily that the 4310 is a bad part, just the the 4110 is an exponentially better part. Is this correct?

 

[eP]

Assume current = 75A, voltage = 65V;
PWM period = 1/17kHz = 58.8ms

For 4110:
Switching loss due to "rise time + fall time" = 65*75* (0.155m/58.8m)/2
= 6.4 W
Rdc(ON) loss = 75*75* 3.7m= 20.8W

For 4310:
Switching loss due to "rise time + fall time" = 65*75* (0.188m/58.8m)/2
= 7.9 W
Rdc(ON) loss = 75*75* 5.6m= 31.5W


The switching loss due to "rise time + fall time" for 4110 is less by 18%
The Rdc(ON) loss for 4110 is less by 36%.

For the ebike application, the Rdc(ON) seems to be the more important parameter for the controller heating and loss.

For 3 phases BLDC controller we have 6 keys and in worsy case 2 of them are ON at the same time so You have to apply 1/3 duty coeff. at the Rdc(ON) loss.
For the same reason only half keys are high side keys so you should divide switching loss by 2 and add to that loss half of loss for the low side keys (diode recovery loss).

The big difference is for 2 FETs per key controllers (which are able to give us such huge currents). In that case we have to divide Rdc(ON) by 2.

At the end we should apply temperature coefficient to Rdc(ON) 1.3 to 1.5.

If we apply all factors above we will see the switching loses are the same important as the Rdc(ON) loses even at 75A current.

At lower currents switchnig loses will be even much more important.

 

[eP]

So then basically there are costs between the two variables on-state resistance vs. voltage. And the 4310 would also have to withstand more voltage in the off-state, and thus generate more heat with less volts, except at full load?

What volts do you mean ? Vds at ON state or at OFF state ?

 

[giveahoot]

I was comparing the non-linear relationship between Rds(on) vs. the V(br)dss. I know that temps play a huge part of Rds(on). In that respect, the 4110 is better in almost every way. I had read it's often incorrectly assumed that Rds(on) and increasing thermal stability also means even current sharing.

 

[eP]

I was comparing the non-linear relationship between Rds(on) vs. the V(br)dss. I know that temps play a huge part of Rds(on). In that respect, the 4110 is better in almost every way. I had read it's often incorrectly assumed that Rds(on) and increasing thermal stability also means even current sharing.

Positive temperature coeff. is helpfull at parallel config.
I think it is discuss for quite different thread.

 

[giveahoot]

I didn't want to cloud the issue. Side-by-side they might be a little more relevant though.

I was just wondering if the greater cost of the 4110 would be offset by a higher quality heatsink on the 4310... or whether the real-world differences are really that much of an issue. I would be interested to see anyone test these two under similar conditions.

 

[The7]

Assume current = 75A, voltage = 65V;
PWM period = 1/17kHz = 58.8ms

For 4110:
Switching loss due to "rise time + fall time" = 65*75* (0.155m/58.8m)/2
= 6.4 W
Rdc(ON) loss = 75*75* 3.7m= 20.8W

For 4310:
Switching loss due to "rise time + fall time" = 65*75* (0.188m/58.8m)/2
= 7.9 W
Rdc(ON) loss = 75*75* 5.6m= 31.5W


The switching loss due to "rise time + fall time" for 4110 is less by 18%
The Rdc(ON) loss for 4110 is less by 36%.

For the ebike application, the Rdc(ON) seems to be the more important parameter for the controller heating and loss.

For 3 phases BLDC controller we have 6 keys and in worsy case 2 of them are ON at the same time so You have to apply 1/3 duty coeff. at the Rdc(ON) loss.
For the same reason only half keys are high side keys so you should divide switching loss by 2 and add to that loss half of loss for the low side keys (diode recovery loss).

The big difference is for 2 FETs per key controllers (which are able to give us such huge currents). In that case we have to divide Rdc(ON) by 2.

At the end we should apply temperature coefficient to Rdc(ON) 1.3 to 1.5.

If we apply all factors above we will see the switching loses are the same important as the Rdc(ON) loses even at 75A current.

At lower currents switchnig loses will be even much more important.

My example is based on simple brushed motor controller with only one FET .
If you apply 1/3 duty (for 3phase BLDC controller) for the Rdc(ON) loss, you should also apply 1/3 duty for the switching loss as well.

Some minor corrections: 0.155ms, 0.188ms and 58.8ms should read as 0.155us, 0.188us and 58.8us (where 1us = 0.000001s)

The stated Rdc(ON) (say 3.7m ohm) is for the current (say 75A) which means an volt-drop(ON) is 0.278V at 75A.
This Rdc(ON) is not linear which means it is not 3.7m ohm at a low current.
In fact, the volt-drop(ON) is more constant than the Rdc(ON) for a wide range of current.

So for two FET in parallel, the Rdc(ON) is not simplily divieded by 2.

 

[eP]

My example is based on simple brushed motor controller with only one FET .
If you apply 1/3 duty (for 3phase BLDC controller) for the Rdc(ON) loss, you should also apply 1/3 duty for the switching loss as well.

Yes. You are right. But for sine waveform we should apply 28% duty for Rdc(ON) loss, so at across all six keys we got 200% switching loss and 170% Rdc(ON) loss (of single key at the same current).

Some minor corrections: 0.155ms, 0.188ms and 58.8ms should read as 0.155us, 0.188us and 58.8us (where 1us = 0.000001s)

The stated Rdc(ON) (say 3.7m ohm) is for the current (say 75A) which means an volt-drop(ON) is 0.278V at 75A.
This Rdc(ON) is not linear which means it is not 3.7m ohm at a low current.
In fact, the volt-drop(ON) is more constant than the Rdc(ON) for a wide range of current.

So for two FET in parallel, the Rdc(ON) is not simplily divieded by 2.

Rdc(ON) is very close to linear at constant temperature in that narrow current range (25A-75A) with tendency to drop below at lower currents side. Look at the fig1. in irfb4110 datasheet.

All above are details. Tell us who will want to use these FETs at 75A current (it is limit for the TO-220 case) ?
Usualy you will want at least two of them for such high limit.
And most of the time you will use no more than 1/3 of that (25A).

So recalculate all above for some realistic case - so will we see if switching loss is important or no.

 

[cadstarsucks]

indeed, as the data he posted shows, the Miller value is higher for the 4310 than it is for the stock 4710 and for the 4110. the values for the 4710 and 4110 are within 10% of each other, while the 4310 is 50% higher.

what this means is that the 4110 is actually a BETTER choice for replacing the stock 4710 than is the 4310. the 4310 will require more current to charge the gate than either the 4710 or the 4110.

Thanks Bob for info.
Now i feel almost as a senior FET advisor :lol:

BTW i hope my previous questions wasn't received by Dan as too offensive and he come back to the forum activity soon.

I do not know what would have been offensive...I am just stressed at work.

Generally the total gate charge ad driver capability determine the FET speed. The Rds will be divided by two but as has been noted the tempco comes into play as well. The dies temp will vary with die dissipation and thermal resistance (how well heat sunk it is). Typically you can expect Rds to be up around 2x at 125C junction temp.

Oh well...back to work

Dan

 

[eP]

I do not know what would have been offensive...I am just stressed at work.

Generally the total gate charge ad driver capability determine the FET speed. The Rds will be divided by two but as has been noted the tempco comes into play as well. The dies temp will vary with die dissipation and thermal resistance (how well heat sunk it is). Typically you can expect Rds to be up around 2x at 125C junction temp.

Oh well...back to work

Dan

When tempco comes into play your proposition (2 x STP for 1x IRFB4110 ) looks like counterproductive.
It was my point.

Regards

 

[cadstarsucks]

When tempco comes into play your proposition (2 x STP for 1x IRFB4110 ) looks like counterproductive.
It was my point.

Regards

IC. Actually while the individual numbers are slightly higher the combination is lower for both Rds and Tr. I believe the combination would be better since the only thing that is worse is the gate charge, which is inconsequential at low frequencies.

From the sheets the Rds is 0.007 instead of 0.005 divided by 2 is 0.0035, TRj-c is 0.5C/W instead of 0.4C/W divided by 2 is 0.25C/W. At 30ADC, for the sake of simplicity, that gives us 3.15W instead of 4.5W (W=I²R) and 0.79C rise from the case to the junction instead of 1.8C (Tr=TRj-c*W).

This is fairly academic, though it sounds like Safe might have some better efficiency numbers from his experiments. Ideally you would measure the instantaneous voltage and current to get the dissipation in the part and measure the case (power tab) with a contact thermometer the calculate the temperature rise to the junction.

Dan

 

[eP]

When tempco comes into play your proposition (2 x STP for 1x IRFB4110 ) looks like counterproductive.
It was my point.

Regards

IC. Actually while the individual numbers are slightly higher the combination is lower for both Rds and Tr. I believe the combination would be better since the only thing that is worse is the gate charge, which is inconsequential at low frequencies.
...
Dan

Not only the gate charge but also miller charge. The last is most important as is triple much higher (triple wore) for 2 x STP combination.

You should begin your estimations from the answer one question: at what current level the swiching loss is the same as the channel resistance loss ?

So it will be clear what we loosing and where, for 2xSTP combination when swiching loss is triple higher. It is not academic discuss it is quite practical.

 

[cadstarsucks]

Not only the gate charge but also miller charge. The last is most important as is triple much higher (triple wore) for 2 x STP combination.

You should begin your estimations from the answer one question: at what current level the swiching loss is the same as the channel resistance loss ?

So it will be clear what we loosing and where, for 2xSTP combination when swiching loss is triple higher. It is not academic discuss it is quite practical.

The total gate charge is slightly more per FET so roughly 500nC instead of 200nC per pulse. At 400Hz (full speed prior to current limiting) 500nC and 96V that is 20mW or 5W at 100KHz. The numbers just do not justify worrying about it.

Dan

 

[eP]

Not only the gate charge but also miller charge. The last is most important as is triple much higher (triple wore) for 2 x STP combination.

You should begin your estimations from the answer one question: at what current level the swiching loss is the same as the channel resistance loss ?

So it will be clear what we loosing and where, for 2xSTP combination when swiching loss is triple higher. It is not academic discuss it is quite practical.

The total gate charge is slightly more per FET so roughly 500nC instead of 200nC per pulse. At 400Hz (full speed prior to current limiting) 500nC and 96V that is 20mW or 5W at 100KHz. The numbers just do not justify worrying about it.

Dan

We don't talk gate charge and gate charge loss, we talking Gate-drain charge and its impact for switching time and consequently swiching loss.

Its quite different area and quite different numbers i'm afraid.

 

[cadstarsucks]

We don't talk gate charge and gate charge loss, we talking Gate-drain charge and its impact for switching time and consequently swiching loss.

Its quite different area and quite different numbers i'm afraid.

I am not surprised that you should be hung up on that, given that the characteristic is you picture...

Nevertheless, the miller charge is the same for the two FETs once you correct for the difference in measurements (50V for the 4110 and 80V for the 4310) and the effective output capacitance is actually lower for the 4310.

That being said the switching losses are effected by the rise and fall times and the drive circuit. These two conveniently use the same drive circuit and show the 4310 to be slower even though the capacitance is lower. The point here becomes that there is more to it than the capacitance since what you are fixated on should, be your statements, make the 4310 faster, but the specs say otherwise.

That all being said, we come back to percentages.

3.5uJ/pulse*F=W (from the 4310 graph for output capacitance stored energy) +

100V*30A*F*(110nS+78nS )/2=W (rise and fall times from 4310 data sheet)

giving switching losses at 400Hz of 0.114W (400Hz is what I have heard the motors run at for max speed) and at 20KHz (20KHz is a guess at the PWM rate for motor current limiting from the controller) of 5.71W for the 4310 and more for the 4110. The question then becomes is this the main contributor to losses or is it conduction?

Did I miss anything?

Dan

 

[eP]

We don't talk gate charge and gate charge loss, we talking Gate-drain charge and its impact for switching time and consequently swiching loss.

Its quite different area and quite different numbers i'm afraid.

I am not surprised that you should be hung up on that, given that the characteristic is you picture...

Nevertheless, the miller charge is the same for the two FETs once you correct for the difference in measurements (50V for the 4110 and 80V for the 4310) and the effective output capacitance is actually lower for the 4310.

Nevertheless, would you like to read the right values for both FETs ?

IC you have some problems, so try to use zoom maybe it could help you to see the true relations.

Did I miss anything?

Dan

Yes you did Dan.

What will be miller charge for 2xSTP config or 4xSTP parallel for replace 2xIRFB4110 config ?
How that charge will affect rise and fall times ?

 

[cadstarsucks]

Yes you did Dan.

What will be miller charge for 2xSTP config or 4xSTP parallel for replace 2xIRFB4110 config ?
How that charge will affect rise and fall times ?

I had forgotten that one...

F*785pF*100V²/2=W (the STP capacitance stored energy) +

100V*15A*F*(90nS+68nS )/2=W (rise and fall times from STP data sheet)

giving switching losses of 244mW/Hz for two STPs in parallel.

The total gate charge and how fast your driver can supply it effects the rise and fall times not the actual miller capacitance. The plateau in the graph that you use is the rise time requiring additional charge in the gate circuit due to the miller capacitance. The faster you can safely supply this charge, the faster the FET switches.

Dan

 

[eP]

Yes you did Dan.

What will be miller charge for 2xSTP config or 4xSTP parallel for replace 2xIRFB4110 config ?
How that charge will affect rise and fall times ?

I had forgotten that one...

F*785pF*100V²/2=W (the STP capacitance stored energy) +

100V*15A*F*(90nS+68nS )/2=W (rise and fall times from STP data sheet)

giving switching losses of 244mW/Hz for two STPs in parallel.

The total gate charge and how fast your driver can supply it effects the rise and fall times not the actual miller capacitance.

Really Dan ?

The plateau in the graph that you use is the rise time requiring additional charge in the gate circuit due to the miller capacitance. The faster you can safely supply this charge, the faster the FET switches.

Dan

So by how many STP FETs parallel we can load the crystalyte controler driver without any impact for rise and fall times ?

Have you any proofs for your original theories ?

Regards

 

[cadstarsucks]

So by how many STP FETs parallel we can load the crystalyte controler driver without any impact for rise and fall times ?

Have you any proofs for your original theories ?

Regards

If you insist...is International Rectifier a reputable enough source?

From AN-944, top of page 3:

"The required gate drive current is derived by simply dividing the gate charge, 15 X 10-9, by the required switching time, 100 X
10-9, giving 150 mA. From this calculation, the designer can further arrive at the drive circuit impedance. If the drive circuit
applies 14 volts to the gate, for instance, then a drive impedance of about 50 ohms would be required. Note that throughout the
“flatâ€￾ part of the switching period (Figure 3), the gate voltage is constant at about 7 volts. The difference between the applied 14
volts and 7 volts is what is available to drive the required current through the drive circuit resistance."

http://www.irf.com/technical-info/appnotes/an-944.pdf

So, as I said, the harder you can safely drive the gate, the faster the FET switches. Interestingly enough, they use the exact graph from all the data sheets which you misinterpret, to prove their point.

The thing that is missing from your interpretation is that the graph only represents time when you are driving the gate with a current source as is done in the fixture when they "measure" that characteristic. It actually only represents a single operating point average of many units.

Dan