Simple BLDC controller

[boostjuice]

Here are some 75v FETs, package current limit for IXFZ520N075T2 isn't listed

From the datasheet;

I(A), TC = 25°C, 200 A = same thing as 'package limit' ?

http://mt-system.ru/documents/ixfz520n075t2.pdf

Are any of those IXYS better than IRFP4368?

There's not a whole lot between them in terms of RDSon. Silicon/wafer current capability is irrelevant unless there is a clear advantage in the package leads current handling capacity.

However, the alternative packages to TO-247/TO-264 do tend to offer slightly lower thermal resistance between Junction>Case & Case>Sink. The key thing is though, that the ones that feature an electrically isolated mounting face offer a more substantial improvement in real-world heat removal performance than a comparison of the summed quoted numbers Rth(JC)+Rth(CS) alone would suggest. The quoted Rth(CS), is for an electrically connected thermal pathway - using thermal grease only to fill the small pores between the metallic interface. For most controllers though, the addition of a silicon pad/Kapton tape must be included for electrical isolation reasons, and the thermal resistance of this is huge compared with the quoted value of Rth(CS).

Models MMIX1F520N075T2, IXFZ520N075T2 IXFN520N075T2 all feature ultra thin, funky chemical, internal electrical isolation between the silicon substrate and the casing thermal interface. So as far as conducting heat out of the wafer and into the heatsink, they don't need a silicon pad/kapton tape and so have a clear advantage over the IRFP4368 and IXFK520N075T2 in terms of staying below their destructive operating temperature at high loading. The problem is, of the better performing packages only the IXFN520N075T2 can be purchased in small quantities from retailers....as far as I can tell.

http://search.digikey.com/scripts/d..._buynow&site=us&lang=en&name=IXFN520N075T2-ND

 

[phyllis]

Thanks - "200A"..

Don't know how I missed that.

On the LED's with unisolated slug it was often enough to use an anodised sink, or some nail polish, or even just sharpie pen...

 

[phyllis]

Here are some 75v FETs, package current limit for IXFZ520N075T2 isn't listed

From the datasheet;

I(A), TC = 25°C, 200 A = same thing as 'package limit' ?

http://mt-system.ru/documents/ixfz520n075t2.pdf

I don't know what it is, but it is not the lead current limit - that is called IL and is listed along with IA in the other datasheets. Possibly avalanche current?
Do the leads usually melt inside or outside the package?

 

[CamLight]

You're right, I(A) is the avalanche current rating. You can see the avalanche energy rating, 3J, just below it.

There's no independent package current limit value for the IXFZ520N075T2, you have to look at the I(D25) rating. This is 465A but ONLY FOR A CASE TEMP OF 25C!!! Since this is impossible for anything other than a single, very short pulse, you have to derate I(D25) as the package heats up.

Check out Figure 6, Drain Current vs. Case Temperature.

 

[texaspyro]

What! A FET maker posting bogo specs... say it ain't so!

 

[phyllis]

You're right, I(A) is the avalanche current rating. You can see the avalanche energy rating, 3J, just below it.

There's no independent package current limit value for the IXFZ520N075T2, you have to look at the I(D25) rating. This is 465A but ONLY FOR A CASE TEMP OF 25C!!! Since this is impossible for anything other than a single, very short pulse, you have to derate I(D25) as the package heats up.

Check out Figure 6, Drain Current vs. Case Temperature.

I see, but that is just a "rating" right, tells me nothing about whether it is the silicon or the leads or the epoxy that can't stand it. It's still over 100 amp more at 100 deg C than 4368 at 25C. It's got a smidge lower on resistance than 4368 and is a bit larger slug area too. I've emailed to ask them where to get a few. I never destroyed big fets before, so it would be interesting.
By "case" I assume they are referring to slug (metal base), and not epoxy...?

EDIT: It seems like fig 6 is just a derating to keep junction temp below the rated 175C. Nothing to do with the legs apparently. If you use Rds on vs temp graph (ie 2.7mOhm @ 175C), and the jc c/w number (0.25), you can plot the same graph.

 

[CamLight]

It really doesn't matter what melts, I guess. The FET is toast.

From what I can tell, there's no independent FET leg or bond wire rating.
You'll easily exceed the max. junction temperature rating though before either of those melt unless you're using very short bursts of current and coming close to I(DM) or I(D25). At a constant 300A, you've got over 110W at the start, rising up to over 220W as it heats up. At I(D25), you've got over 500W!

Considering the difficulty in cooling FETs creating that much heat pretty well insures that the junction will probably melt long anything else does.

 

[rhitee05]

Unless it specifically says otherwise, the data sheet ratings are usually silicon ratings. Sometimes they include a package or a lead limit, sometimes they don't. IRF I know has a number of separate papers written on package limits and so forth which provide a lot of relevant info, IXYS probably has something similar. The ratings are also usually given under certain conditions which may or may not be realistic, so you have to interpret them according to the application conditions. Taking datasheet ratings at face value is rarely useful without some deeper analysis.

 

[phyllis]

It really doesn't matter what melts, I guess. The FET is toast.

Well, I want to know. Also, it matters if you want to push the FET, you need to know what is the failure point. That is why I asked about the TO legs. If the legs are a problem, pull the heat from them with fat wires close to the epoxy, or clamp them straight to the sink.

From what I can tell, there's no independent FET leg or bond wire rating.
You'll easily exceed the max. junction temperature rating though before either of those melt unless you're using very short bursts of current and coming close to I(DM) or I(D25). At a constant 300A, you've got over 110W at the start, rising up to over 220W as it heats up. At I(D25), you've got over 500W!

Considering the difficulty in cooling FETs creating that much heat pretty well insures that the junction will probably melt long anything else does.

Probably.

 

[CamLight]

It really doesn't matter what melts, I guess. The FET is toast.

Well, I want to know.

You're going to have to ask the manufacturer about the failure points for that FET then.
Since the wide legs on that FET obviously have to narrow down considerably as the legs approach the junction, that creates a bottleneck for heat buildup. I'm guessing that this bottleneck (whether bond wire or metal soldered to the die) will fail before the legs do.

Also, it matters if you want to push the FET, you need to know what is the failure point. That is why I asked about the TO legs. If the legs are a problem, pull the heat from them with fat wires close to the epoxy, or clamp them straight to the sink.

In my experience, the bond wires fail before the legs do in TO-cased FETs. But, it all depends on how far you exceed the ratings. Go far enough and both can be damaged, with one just beating out the other to failure. PCB layout and the amount of copper (area and copper trace weight) has a HUGE effect on the leg temperature too. This is critical to keeping the legs from becoming unsoldered. But, if they do come unsoldered, you've exceeded the max FET temperature but so much that FET junction failure will come soon anyway, way before the legs melt.

If you want to exceed TO-cased FET current ratings (which will probably also exceed the junction max. temperature rating) then heat-sinking the legs (via lots of PCB copper, soldered on wires, or clamping to metal) will cool both the legs and the bond wires. Cooling the FET case via it's rear plate cools the bond wires too. Heat is being removed from the junction of the FET, which also pulls heat from the bond wires.

FETs also fail quite often from thermal fatigue. This happens when the FET is heated up and cooled off hundreds of times, gradually loosening bonds between the different parts of the FET, leading to increased internal resistance, admittance of moisture, oxidation, and eventual failure. This happens at temperatures and current levels WAY below the max. ratings.

 

[texaspyro]

I've found that bond wires almost always fail before legs.

 

[phyllis]

<snip>
Since the wide legs on that FET obviously have to narrow down considerably as the legs approach the junction, that creates a bottleneck for heat buildup. I'm guessing that this bottleneck (whether bond wire or metal soldered to the die) will fail before the legs do.

Probably narrowing down a bit, but aren't these chips quite huge, covering most of the base plate?

In my experience, the bond wires fail before the legs do in TO-cased FETs. thanks But, it all depends on how far you exceed the ratings. Go far enough and both can be damaged, with one just beating out the other to failure. PCB layout and the amount of copper (area and copper trace weight) has a HUGE effect on the leg temperature too. This is critical to keeping the legs from becoming unsoldered. But, if they do come unsoldered, you've exceeded the max FET temperature but so much that FET junction failure will come soon anyway, way before the legs melt.

If you want to exceed TO-cased FET current ratings (which will probably also exceed the junction max. temperature rating) then heat-sinking the legs (via lots of PCB copper, soldered on wires, or clamping to metal) will cool both the legs and the bond wires. Cooling the FET case via it's rear plate cools the bond wires too. Heat is being removed from the junction of the FET, which also pulls heat from the bond wires.

FETs also fail quite often from thermal fatigue. This happens when the FET is heated up and cooled off hundreds of times, gradually loosening bonds between the different parts of the FET, leading to increased internal resistance, admittance of moisture, oxidation, and eventual failure. This happens at temperatures and current levels WAY below the max. ratings.

I'm not thinking about using PCB, but sandwiching a waterblock between two layers of FETs.

 

[phyllis]

I've found that bond wires almost always fail before legs.

Is there space for more wires?

 

[CamLight]

<snip>
Since the wide legs on that FET obviously have to narrow down considerably as the legs approach the junction, that creates a bottleneck for heat buildup. I'm guessing that this bottleneck (whether bond wire or metal soldered to the die) will fail before the legs do.

Probably narrowing down a bit, but aren't these chips quite huge, covering most of the base plate?

Perhaps for that package type, but for some DCB FETs the die is still pretty small compared to the very large case so I don't know:
http://www.ixyspower.com/images/technical_support/Application%20Notes%20By%20Topic/Isolation%20Techniques,%20Mounting,%20Soldering%20and%20Cooling/IXAN0026.pdf
http://www.ixyspower.com/images/technical_support/Application%20Notes%20By%20Topic/Power%20Semiconductor%20Quality%20Assurance%20and%20Testing/IXAN0045.pdf
The extra room is used as a heat spreader to lower the junction-to-sink resistance.

The larger the die, the more expensive it is to manufacture and the harder it is to ensure that the current and temperature is evenly distributed across the die. As the on-state resistance of the IXFZ520N075T2 is about 1mOhm or so, the die can't be much larger than other dies that have a similar resistance spec. Using multiple bond wires and a DCB substrate for the die lets them significantly increase the current rating, and decrease the thermal resistance, for an already existing die.

With an I(D25) of 465A, there's obviously a very good connection between the tabs and die. But, with good thermal characteristics a lot of that increase over another package type can be done without having a larger die.

it's certainly worth trying to contact tech support at IXYS and see if they can get you the dimensional data for the die they used. A lot of manufacturers purchase just the FET die and package it themselves so the info should be available.

 

[CamLight]

I'm not thinking about using PCB, but sandwiching a waterblock between two layers of FETs.

If no PCB, were you going to connect the FET legs via direct soldering of the wire to the legs?
Always risky (can come unsoldered, hard to safely solder them on, etc.), but it can remove more heat than a PCB depending on how long the wires are, their gauge, and what kind of PCB layout you're comparing it to. Looking forward to seeing your setup as you get it up and running!

 

[phyllis]

Thanks again, those look like the kind of papers I was looking for (but not hard enough). I did find IXYS' chip catalog, they don't list the good chips, but some of the ones they list are relatively large compared to their package. You're saying that small chips have less Rdson - that is counter-intuitive.

If I can get the FZ package, I would place the phase leads (flippers) on top of each other, and a copper plate underneath. Solder the three together, and glue the plate to the copper sink. The +Ve and ground flippers would curl around the side of the sink and meet the other FET pair's flippers (12 fets). The +Ve and ground bus bars would snug underneath those flippers and be glued to the side of the sink.
So as long as there is water in the sink the solder can not melt.
Something like this:

 

[CamLight]

<snip> You're saying that small chips have less Rdson - that is counter-intuitive.

Didn't say that.
I said that the IXFZ520N075T2 die couldn't be a lot larger (than other 1mOhm dies) since the on-state resistance spec is about the same as other smaller-cased FET dies with low Rds(on) around 1mOhm.

If I can get the FZ package, I would place the phase leads (flippers) on top of each other, and a copper plate underneath. Solder the three together, and glue the plate to the copper sink. The +Ve and ground flippers would curl around the side of the sink and meet the other FET pair's flippers (12 fets). The +Ve and ground bus bars would snug underneath those flippers and be glued to the side of the sink.
So as long as there is water in the sink the solder can not melt.
[/attachment]

Well, the solder can certainly melt if the water doesn't remove enough heat.
Water-cooling can often be good at removing heat from point sources but it takes a lot of good design (and tons of other stuff like piping, fans, maintenance of the system, etc.) to do the job well. You've got a very interesting setup for the FETs, one I've never seen before, and I'm really looking forward to seeing it come together and hear your reports!

 

[x88x]

Any recent developments on this controller?

 

[liveforphysics]

I've found that bond wires almost always fail before legs.

Weird.

For me, it seems like if it happens as a slow over current event that gradually heats up I pop the bond wire of the source side, so it bubbles the case up and lets the magic smoke out on the lower right corner of the epoxy block.

If it's a rapid over-current event, it seems to be about a 50-50 mix of the leg popping like a fuse or the die itself exploding and cracking the case.

 

[texaspyro]

I count die meltdown as bond failures... but then my most common failure is the die turns to a rather nice short circuit with the bond wires/legs still intact. Very seldom do I have a leg fuse.

 

[nieles]

hi jeremy,

did you have a chance to test the controller ohter than some no-load testing?
could you post some pictures?

i finaly mastered the art of etching a pcb!
so i can finaly build one of these controllers.

if there is interest, i can organise a group buy for the needed parts (europe only probably)
(minus the MC33033 Chip, i can only find the through hole part on ebay)

 

[x88x]

I've been wondering about this too. This thread was all abuzz a month or so ago, and then suddenly nothing. It didn't get shelved, did it?

 

[Alan B]

Jeremy has been having an internet issue causing difficulty accessing ES for the past couple of weeks. Hopefully he will be back shortly.

 

[x88x]

Jeremy has been having an internet issue causing difficulty accessing ES for the past couple of weeks. Hopefully he will be back shortly.

Ah, ok. Thanks for the info.

 

[J-aprilia-N]

why is it still on this topic :|