eBike Master Switch Design

Thanks for pointing that out Richard.

It is not totally straightforward as the load on the FETs is not constant voltage for the whole turn-on period. It is constant current, but the voltage plummets, and there are four FETs in parallel that are hopefully sharing the current (not guaranteed at all though).

So for good reliability it is prudent to slow down on the higher voltage setups, depending on the number of parallel FETs. As we work through the details we'll come up with some rules of thumb and recommended values for components.

Sounds great on the Zeners and low current operation. I've had problems with low voltage zeners, but higher voltage types are much better - they are a different type of diode.
 
I pulled up a different data sheet on the 4110, and the SOA graph goes to lower currents. It indicates that at 100V the safe current is limited to 100mA for DC, and 100mS is pretty much DC. :shock:

http://www.irf.com/product-info/datasheets/data/irfb4110pbf.pdf

I tried to get some relief from the dropping voltage, but it doesn't drop fast enough to help much. So to remain in the safe operating area the DC value would be recommended.

So this would indicate, for a 4,000uF controller at 100V with 4 parallel 4110's (assuming the current sharing is ideal):

Each FET is effectively charging 1,000uF at 100V,
Safe DC Current is 100mA,

i = C * dV/dT

0.1 = 1,000*10^-6 * dV/dT
so dV/dT = 100 V/s
and 1 second is recommended if the FETs are perfectly dividing the current,
so 2 seconds would be recommended for margin

So 1 meg R1/R2 and 2uF.

Perhaps I'll make more room for the capacitor setup, and SMT starts looking very attractive. :)

Note that controllers with less capacitance will not need such a long on-ramp time. So it would be good to know the capacitance of your controller when setting up a master switch. Also using more FETs in parallel helps.

It would not be hard to put eight FETs on this board by piggybacking four on top of the first four. A strip of aluminum on top of the tabs with holes allows the two rows to be thermally and physically connected, and the leads of the top FETs bent down and soldered to the leads of the lower FET. These top FETs will not be quite as low impedance as the lower set, but they will help significantly. This will be especially important for 4115 setups at higher voltages.

So, 100mS may be fine for some setups, but not for all. It depends on the caps in the controller, the voltage, and the number and type of FETs used.
 
Alan B said:
Perhaps I'll make more room for the capacitor setup, and SMT starts looking very attractive. :)
Click to expand...
Ya - but many potential buyers of the board might be put off - unless you are looking to sell populated boards, I think you will find a larger audience with continued use of thru-hole components to keep the fabrication bar as low as possible. Just another small intrusion of market considerations into technical considerations....
 
The SMT capacitor will be pretty big, so not hard to hand solder. There is just more selection available in SMT parts.

I think the SOA curve on the graph is pretty conservative. Arlo1 tried a single 4115 on his setup (contactor driver) and it survives precharging despite being quite a ways outside the safe area.

Stacking the FETs is a good way to get more into a small package. Since the current sharing won't be equal, it won't double the rating but you might get 1.5x or more. I tried this on my D126 BMS active cutoff. Double Stacked 4110s.jpg
 
I will set the PCB up for either SMT or through hole caps, and has as been mentioned a couple times, these SMT caps are large and not hard to solder with a regular soldering pencil! When I do a parts search for this I find ten or a hundred SMT parts for every leaded part, so we might want the option!

Stacking FETs - great photo. I did it long ago and have no photo of it (that I recall), so excellent photo! That is just what I was thinking of, perhaps with the aluminum strip not sticking out so it would still fit in the box, but if there's room then sticking it out is fine - except watch out when the switch is off that heatsink rises up to +battery voltage! :shock:
 
Alan, THX for your time and your calculations. I'm not an electrical technician and i like that you explain.

In my Controller there are about seven 470µF caps + four 470µF more in my Master switch case (all low esr). That makes together about 5200µF capacitance.
My Battery is 90V hot off the charger. The master switch is made up of four IRFP4468PBF TO-247 FET's.

Can you tell me if the precharge process will be safe with 1M resistor, 1µF cap or should i better use other parts?

PS: a water resistant hammond box would be even more nice :)
 
I suspect you are okay (without having done more calculations). You have bigger FETs and not much more capacitance, so you are in the ballpark at least.

You will probably not want to turn it on twice in a row quickly though, those FETs may still be hot from the first cycle.

*update* see below, there are questions.
 
madin88 said:
My Battery is 90V hot off the charger. The master switch is made up of four IRFP4468PBF TO-247 FET's.

Can you tell me if the precharge process will be safe with 1M resistor, 1µF cap or should i better use other parts?
Click to expand...

The safe operation area for those FETs is huge. You'll have no problem. Even a single one won't come close to blowing during precharge. The TO-247 package can handle much higher peak dissipation than a TO-220.
 
fechter said:
The safe operation area for those FETs is huge. You'll have no problem. Even a single one won't come close to blowing during precharge. The TO-247 package can handle much higher peak dissipation than a TO-220.
Click to expand...

that sounds good. thx.

My water resistant master switch electronic box (with power supply) is completed and now i will go and test it.
If nothing blow up and everything works how it should, i will post some pics..
 
Well, I should have looked at the datasheet before commenting.

The IRFP4468 safe operating area looks worse than the IRFB4110, if I'm reading this datasheet right. At 0.1A it only barely gets to 40V whereas the 4110 reaches 100V for DC operation.

http://www.irf.com/product-info/datasheets/data/irfp4468pbf.pdf

http://www.irf.com/product-info/datasheets/data/irfb4110pbf.pdf

figure 8 in each datasheet, Maximum Safe Operating Area.
 
Alan B said:
Well, I should have looked at the datasheet before commenting.

The IRFP4468 safe operating area looks worse than the IRFB4110, if I'm reading this datasheet right. At 0.1A it only barely gets to 40V whereas the 4110 reaches 100V for DC operation.

http://www.irf.com/product-info/datasheets/data/irfp4468pbf.pdf

http://www.irf.com/product-info/datasheets/data/irfb4110pbf.pdf

figure 8 in each datasheet, Maximum Safe Operating Area.
Click to expand...

now i'm confused :shock:

Alan B, Fechter, i'm unfortunately not able to interpret the Fig 8 in the Datasheets. What does this mean for my IRFP4468pbf switch?
 
I am also confused, perhaps Richard will comment, but the 4468 looks surprisingly weak in the Safe Operating Area graph at DC. If we look at the 100V safe current for DC operation, on the 4468 it doesn't even get there at 0.1A, I read it as only barely 40V at 0.1A DC. On the 4110 it was 100V at 0.1A DC. I didn't expect that. In other areas the 4468 appears better, I wonder if there is a problem with that graph? Or if the package has a heat flow problem, the various pulse width downslopes are quite separated, much more than the 4110's.
 
OK, I added two large surface mount cap positions to the board, for 2225 caps, so we can parallel them if needed. One is on each side of the board, it is getting quite tight in there.

The discussion about turn on delay doesn't affect the PC board design as long as we can get enough capacitance and use high valued resistors. One problem is the current through the LED which is in the trigger circuit will also be low at these low currents. The LED could be moved to the output circuit but this will add more parts to the board. :(

I haven't tried 50uA through a low current LED, but this might happen with a 48V system and a 1 meg ohm resistor. Any one try that already?
 
Alan B said:
I am also confused, perhaps Richard will comment, but the 4468 looks surprisingly weak in the Safe Operating Area graph at DC. If we look at the 100V safe current for DC operation, on the 4468 it doesn't even get there at 0.1A, I read it as only barely 40V at 0.1A DC. On the 4110 it was 100V at 0.1A DC. I didn't expect that. In other areas the 4468 appears better, I wonder if there is a problem with that graph? Or if the package has a heat flow problem, the various pulse width downslopes are quite separated, much more than the 4110's.
Click to expand...

ok, so this means 1sec delay time with 5000µF capacitance is to fast and will cause in lots of heat in this 4468 FET's :?
I haven't test my switch for so far and now i'm very afraid to blow it up..

Alan, i hope its ok for you that i post in your thread about my problems.

btw: i'm in for an order if the new boards are out
 
Ah, my bad. I was in a hurry and misread the graph.

Still, based on testing by others, I think a 1sec charge time is going to be OK, especially with 4 parallel.

I think the limitations in the SOA graph are based on how fast heat can get from the silicon to the heat sink tab. Even with 10,000uF at 100v, the total amount of heat the transistor is going to thow off is minimal during precharge. Still, if the precharge current is too high, we know it can release all the stored up smoke inside the FETs.

If the SOA graph was really right, Arlo1 would have blown his up 4115s instantly, but they work.
Maybe they put a lot of 'safety factor' into that side of the graph. I find it sort of hard to belive you couldn't safely pass 0.1A @ 100v (10W dissipation) through one of those big TO-247 things for one second.
 
Capacitor Charging 101

The energy dissipated in the charging circuit resistance (here mostly the FETs) equals the energy in the capacitor. Surprising, but true.

Energy in the Capacitor:

E = 1/2 * C * V^2

So 1/2 * 10,000uF * 100^2 = 50 watt-seconds or 50 J.

So this same energy will be dissipated in the charging circuit. Spread over the several FETs, wires, etc in the circuit. Mostly in the FETs, and not totally evenly balanced.

It doesn't matter how quickly the charging is done, the energy is the same. So it is just a matter of how much time this energy is spread over.
 
Second Round of Boards (V1.1)

This posting will be updated as work progresses, BOM, notes etc here. Refer to this posting for updates on this revision of the boards. Plan to make six boards in this round. Up to five will be available for beta testing. This is a work in progress.

Updated Design, out for fab:

0) Sized to fit in Hammond box
1) Thermal vias re-added
2) Cleared more trace area on rear for copper buildup
3) Increased spacing for voltage
4) Moved silkscreen slightly (did not update renders here to show that)
5) 6 boards ordered 11/25/2013 830pm, approx 2 weeks turnaround
6) Boards sent to fab 11/26, estimated back from fab 12/8, plus shipping to me
7) Boards at OSH Park 12/4, enroute to me 12/4

Front

ebike%2520master%2520switch%25201.1.png


Rear

ebike%2520master%2520switch%25201.1r.png


Schematic

Ebike%2520Master%2520Switch%2520PCB%2520Schematic%25202.02.png


Preliminary BOM

R1,R2 1M nominal 1/4w (all resistors 1/4w unless otherwise noted)
R3 10K (was 1K)
R4-7 1K or insulated wire jumpers
C1-3 1uF (NonPolar) nominal at full battery voltage (plus 20% safety margin), 3 sites for convenient parallel configuration (see discussion for more details)
D1 12V zener
D2,3 1N4148
Q1-4 Main FETs, nominally for 90V: IRFP4110PBF (quantity to be determined by current handling required)
Q5 TP2104N3-G or ZVP4105A; TO92 P channel FET low voltage gate (max gate on-threshold voltage should be less than minimum gate on-threshold for main FETs, max voltage 20V)(TO92 pinout SGD, S toward D2)

Enclosure Hammond 1551K

J1 pin 1 -battery (for BMS)
J1 pin 2 +battery turns on
J1 pin 3 -controller (for BMS)

one wire in and out per FET
B- wires, 4 each #12 to battery negative
C- wires, 4 each #12 to controller negative

WARNING - high voltages present from battery, potentially lethal, take appropriate safety measures, DO NOT TOUCH when power is connected

document in work, not complete yet, refer to earlier board for some details but realize this board is slightly different

---

izeman's component values for a 75V version (see page 12)

Code: 
R1,R2 100k nominal 1/2w
R3    10K
R4-7  1K
C1-3  1uF (NonPolar) 100v - one C installed on the upper side of the board @C1
D1    12V zener
D2,3  1N4148
Q1-4  Main FETs, nominally for 75V: IRFP3077 - installed @Q1+2 only
Q5    2N3906
 
why there must be both controller - and battery - on the J1 switch connector?
Battery + will be connected to the (key)switch separately right?

My master switch with big IRFP4468 works fine :) Big thx Alan and Richard for your nice circuit and help.

here some pics of my switch with power supply and charging plug in waterproof hammond box: http://endless-sphere.com/forums/viewtopic.php?f=6&t=53867&p=825361#p825361
 
madin88 said:
why there must be both controller - and battery - on the J1 switch connector?
Battery + will be connected to the (key)switch separately right?

My master switch with big IRFP4468 works fine :) Big thx Alan and Richard for your nice circuit and help.

here some pics of my switch with power supply and charging plug in waterproof hammond box: http://endless-sphere.com/forums/viewtopic.php?f=6&t=53867&p=825361#p825361
Click to expand...

My system cabling plans call for the other lines, I think the BMS needs them. They aren't needed for the keyswitch operation, which does need B+. I thought about routing B+ through this board, but decided not to. Trying to plan for the future. :)

Great on your switch!
 
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