low inductance output stage contruction

[whereswally606]

I was thinking this the other day when bobc and I were looking over the design of the driver board. It's not good to hard parallel in that stack of mti85w100c as you don't know how closely matches the fets are between different chips. But say you use 3 mti85w100 one on each phase. That gives 12kwh. You could do this twice and split the phase wires so you have a 6 phase motor and boom 24kw for £80



this is one of the 12kw power stages in virtual form

 

[bobc]

bit more guff..... Within a module there is no guarantee of good matching either, but there is a high probability that the individual MOSFET devices are from the same batch or even wafer. Hard paralleled mismatched switches - the slowest one gets all the turn-off losses and the fastest one all the turn on losses. Conduction losses share pretty well in FETs, 2nd breakdown is unlikely, it's the switching losses that get you.
Andy - those are REALLY small fans you drew, like 25mm - you won't blow off 40W with one that size. I'd have thought you wouldn't bother with a fan - isn't this thing doing 60mph....?? Long duration high current at low speed is going up an alp - you won't be doing much of that will you?

 

[Arlo1]

bit more guff..... Within a module there is no guarantee of good matching either, but there is a high probability that the individual MOSFET devices are from the same batch or even wafer. Hard paralleled mismatched switches - the slowest one gets all the turn-off losses and the fastest one all the turn on losses. Conduction losses share pretty well in FETs, 2nd breakdown is unlikely, it's the switching losses that get you.
Andy - those are REALLY small fans you drew, like 25mm - you won't blow off 40W with one that size. I'd have thought you wouldn't bother with a fan - isn't this thing doing 60mph....?? Long duration high current at low speed is going up an alp - you won't be doing much of that will you?

There is no slow or fast fet the miller plateau is at slightly different voltages. So the fet with the lowest gate threshold will have the highest switching losses. But as it heats up its gate threshold increses.

 

[whereswally606]

My issue is that its going to be tough to place the powerstage in a position on the scooter that gets the 60mph airflow. I might therefore look again at water cooling and putting the radiator at the front of the scooter behind the front wheel, there was a chap in china doing similar things with his scooter which looks promising. One place it could go is right underneath the scooter at the back of the battery box if I can make it slim enough, slightly sloped to get forced air directly over the heat sinks.





this is as far as I've got mentally with it.

 

[bobc]

Andy,
you need about 0.5 k/W from your heatsink. Take a look at the heatsinks section on the RS to see what sort of size that performance requires. You might get some inspiration there too, but it will certainly give you a better idea what you need to be sketching (some of your sketches look a bit small in he heatsink department...)
There are other specialist heatsink suppliers, but they can be tricky to get stuff from. The catalogs are very convenient (if they have something suitable)

 

[whereswally606]

Looked at RS for heatsink for 0.5k/w but found nothing which looked good for the IsoPlus Dil package i.e. 37.5 x 25mm.

Anyway I feel like I've unwittingly hijacked Lebowski's thread, at first I was just developing ideas on different physical layouts of Lebowski's original idea but now the posts seem to be moving on to the actual design of a power stage specifically for my E-max scooter. I'm going to propose that if people are following that then I will continue to post in my thread here:

https://endless-sphere.com/forums/viewtopic.php?f=10&t=80468

My apologies for going off at a tangent and thanks again to those people helping me from creating a poorly thought out power stage.

 

[Lebowski]

So now I have this test setup for trying out different gate resistors:

I only use one channel, it is loaded with a resistor and big inductor in series to the positive supply. This way a current will flow into the controller, the consequence of this is that the low side FET controls both the rising and falling edge.

I use the controller IC with a roughly 80% dutycycle output, with my resistor etc etc this maxes out my power supply. I didn't measure the phase current directly, but the supply delivers 150W in 0.66 Ohm, so phase current is roughly 15A .

This is the turn on for 10 Ohm off resistance and 10+27 Ohm on resistance:
(gate in yellow, drain in magenta)

You can see the miller plateau lasts about 300 nsec, quite long (this is the time during which the FETs has switching losses).
Also, from the gate trace you can see that it takes about 300nsec to reach the FETs threshold level.
and the turn off:

The gate shows it takes around 500nsec to reach the miller plateau, and then another 400 nsec on the miller plateau before finally the FET is off and the output has reached the supply. Because the output slope is pretty relaxed there is little overshoot.

A 500 nsec deadtime with these resistors is tight as the current carrying FET takes 900 nsec to switch off. The FET turning on has 500nsec deadtime delay and 300 nsec to reach threshold, so it is already conducting before the other FET is off.

 

[Lebowski]

This is the turn on for 4.7Ohm off resistance and 15+4.7 Ohm on resistance:

It takes 200 nsec to reach the miller plateau, which in turn lasts about 200 nsec.

The turn off:

Here to reach the miller plateau takes around 300 nsec, the miller plateau takes 200 nsec.

With these resistors the current carrying FET takes 500 nsec to switch off, the other FET takes 200 nsec to turn on (to start taking current).

A 500 nsec deadtime is doable as the current carrying FET is already off by the time the deadtime is over, there is a 200nsec margin.

Note that the faster turn-off results in a higher overshoot than with the higher gate resistors.

 

[bdj]

Hello.
I had a lot problems with my earlier setup. So I tried setup with copper plates and here are results.
Also I have huge ringing. Turn on and turn off resistance is same 12R.
Power supply is battery 12V and 24V.
Configuration half bridge, motor connected between ground and common node D-S.

Fets irfp4668
gate driver irs21867s
DC cap is 0.68uf https://www.mikroprinc.com/uploads/store/products/pdf/r46cmkp_pdf5b57090e7015f.pdf

 

[peters]

Hello.
I had a lot problems with my earlier setup. So I tried setup with copper plates and here are results.
Also I have huge ringing. Turn on and turn off resistance is same 12R.
Power supply is battery 12V and 24V.
Configuration half bridge, motor connected between ground and common node D-S.

Fets irfp4668
gate driver irs21867s
DC cap is 0.68uf https://www.mikroprinc.com/uploads/store/products/pdf/r46cmkp_pdf5b57090e7015f.pdf

Hello!
This ringing is between the Coss of a FET and the loop inductance that consists of the 2 FETs, the bus bars and the ESL of the DCbus capacitor. An RC snubber can fully eliminate it, here is an app note: https://statics.cirrus.com/pubs/appNote/AN0454REV1.pdf
But they miss a few points: they just choose the Csn to be 3 times of the Coss, but Csn should be selected so that the cutoff frequency of the snubber (as a low-pass filter) is significantly lower than the ringing frequency, so that there is no ringing on Csn at all. No need to measure Coss, it is in the capacitance vs. Vds figure in the datasheet, because Coss changes with the voltage. Also the snubber is most effective close to the Coss of the FETs, so it is better to place one on every FET D-S (2 snubbers for a half-bridge).
You can also reduce the loop inductance even more: move the output wires outside the copper plates and move the plates closer, put an insulator sheet between them, or just replace the copper plates with a double sided PCB.

 

[bdj]

Yes you are right. Earlier I tried with snubber. After couple of tries get the right values and all ringign was gone. It was just for a test. I will check a link you posted.
But I was hoping some other soulution. The fet is more-less similiar with fet used in this thread from beginning. And clean Vds can be seen on page 1 without using snubbers just dc link, fets and gate signals. So almost same set up.
I will try to place copper sheets as you suggested.
Shouldn’t be possible to get clean Vds without ringing and without snubbers?
Maybe I have issue with impedance of small cap I used 0.68uF? Type is metallized polypropylene film capacitor. Below is chart from datasheet.

 

[peters]

From the graph the ESL of this cap is probably between 10 and 15nH, that could be reduced with more parallel capacitors. Measure the DC bus voltage with the scope at the capacitor, there should be no or only a small ringing, then you'll see if more or bigger caps are needed.
The loop inductance and the Coss is an almost undamped LC circuit that naturally oscillate, I think Lebowski's measurement on page 1 was without or at very low current. All circuits I've seen with different kinds of FETs oscillated more or less without a snubber. Lower loop inductance is always better because that stores less remnant energy after the transition.

Another thing to consider is that the oscilloscope may display higher ringing amplitude than it really is, for two reasons:
- the loop at the end of the probe (long gnd wire) picks up the radiated magnetic noise from the current switching nodes at the FETs.
- the common-mode rejection of the single-ended scope input may not be high enough at the ringing frequency, and then it displays the common-mode voltage also, not only the differential voltage.
But in either case the ringing is there in the circuit, just the real amplitude is possibly lower.

Slower FET turn-on and turn-off also reduces the ringing:
- change to a higher gate resistance
- add an external gate-source capacitor (equal or less than the internal Cgs of the FET) with a small serial resistor. It looks like a "snubber" between the gate and the source, but it is a negative feedback from the voltage on the FET source inductance (Ls*dI/dt) to the gate voltage, that limits the slope of the current transitions. There may be optimal C and R values for the lowest ringing amplitude, but I haven't figured that out yet.

 

[bdj]

Here is picture of dc link pretty high ripple and adding parallel capacitors reduce ripple with small percent. Lower cap values does better job then higher values above 1uF don’t have much influence.

As understood from text I think he tested with “good” current and higher voltage. My idea was to produce similar results but there is a lot of differences.

Yes concerning undamped oscillation is true but I was hoping that ringing would be lower not to reach 3 times power supply.
Concerning scope issues, for measurement of Vds didn’t use long gnd clip, I use shorted version something like this that can only address first issue.

Concerning slowing down things with bigger gate resistors how much fall time would be acceptable for start point? 1uS? I saw in some IPM modules rise and fall times is more than 1us.
I will also test last suggestion. I have only experimented with parallel caps to gs. Result in smoother Vgs, slower turn on-off times and I would say little safer against parasit turn on?

 

[peters]

Lebowski's waveforms above your first post is from another design:
https://endless-sphere.com/forums/viewtopic.php?f=30&t=91689
There are some more reference waveforms, too.
For realistic comparison you'd also need a 65V power supply, because then the FET capacitances are lower, the ringing frequency is higher, and the relative ringing amplitude is lower, and maybe the absolute, too.

Concerning the rise and fall times, for TO-247 without snubber I'd say the Vgs fall time is min. 1us and the Vgs rise time until the end of the Miller-plateau is also min. 1us, so the total gate rise time is 3-4 us. The Vds edges are faster. The highest ringing amplitude, as you also saw, is on the low side FET Vds after the reverse recovery, because then the high side FET changes to a new operating point very quickly (lower Id, Vgs and Vds at the same time), and the low side Vds shoots out.
With Vds snubbers the timings can be faster.
External Cgs also slows down the Vgs and the current rise and fall times, but it forms an undamped loop with the internal Cgs and the Ls, so normally I prefer to add a serial resistor.

As there is voltage oscillation on the DC bus, you can also try a DC bus snubber next to the FETs, that should also reduce the ringings on the FET Vgs and Vds, but does not increase the switching loss.

 

[zombiess]

You should get less ringing if you put your DC bus copper bus bars closer together as it will reduce the loop area and allow for more EMF cancellation. Magnetic fields fall off at 1/r^2, so the closer together, the better the cancellation. I would put a piece of Kapton/polyamide tape on each one and secure them together, then resolder the parts.

As for switching times, i have some paralleled irfp4568s which have a Vds on/off times of about 100ns (waaay too fast and im slowing them down to 300ish ns), and no snubber. The big difference is my DC bus is has a tiny loop area as i made it with 4 layers of a 6 layer PCB. I measured the parasitic DC bus inductance to be just under 20nH. I've put 600A pulses through the bus and it has minimal ring, but does get a sizeable turn off overshoot spike at this crazy fast switching speed. I had to add 10nF of additional G-S capacitance to slow it down to 300ns as changing the gate resistor from 10ohms to 20ohms barely made a difference. A small amount of G-S cap will also help dampen ring as it alters the Cgs vs Cgs ratio, but you only want to add as little as needed.

As your plates move together, you should see the ringing freq increase and amplitude drop.

Your ringing amplitude should also reduce as you increase DC bus V. When testing it's best to keep the DC V > Vgs as the ringing wave form can drop below the miller plateau. This could setup an oscillation. I don't pulse test below 20V

 

[peters]

As for switching times, i have some paralleled irfp4568s which have a Vds on/off times of about 100ns (waaay too fast and im slowing them down to 300ish ns), and no snubber. The big difference is my DC bus is has a tiny loop area as i made it with 4 layers of a 6 layer PCB. I measured the parasitic DC bus inductance to be just under 20nH. I've put 600A pulses through the bus and it has minimal ring, but does get a sizeable turn off overshoot spike at this crazy fast switching speed. I had to add 10nF of additional G-S capacitance to slow it down to 300ns as changing the gate resistor from 10ohms to 20ohms barely made a difference. A small amount of G-S cap will also help dampen ring as it alters the Cgs vs Cgs ratio, but you only want to add as little as needed.

My layout is different, but also under 20nH: rings at ~40MHz at 60V with Coss=0.9nF (4568), though I prefer to switch faster that comes with high amplitudes. The inductance couldn't be much lower because most of it is of the TO247s.
I think the difference that suppresses the ringing on your board is something else, maybe the position of the external Cgs? Where did you place it exactly on the power board?

 

[zombiess]

Peters, my post was directed at bdj. I'm unaware of what your layout looks like.

 

[peters]

Peters, my post was directed at bdj. I'm unaware of what your layout looks like.

That was clear, but I wanted to add that another boards I have with similar inductances ring, so my conclusion is that low inductance alone is not the key to eliminate the ringing.
I think it is the added Cgs that makes a big difference if it is placed in a specific location, that's why I'm wondering where did you place it on your board?

(My layout is another story, I'll start a thread for that.)

 

[bdj]

Thank you both for detail guide.
Currently I had only battery with 12V with high current capacity but soon I will test with higher voltage and added cap and post results.
Here is new setup with tape, closer plates and pictures of ringing.


Tested it with higher current then before, now it is 33A. Yes it reduced ringing a lot.
Next picture is Vgs. Yes it is falling below treshold and can switch off fet easily.

Soon I will test adding C to GS and with higher voltages. Can higher voltage reduce a lot ringing because as see from datasheet output capcitance falls very quickly with higher supply voltage? Is your lauout with 6 lyers availbale on forum? From pictures how would you read rise time, time until reach full gate voltage or time until passes some value above treshold which provides me desired current?
Shouldn’t be surface of DC two copper plates be as big as possible because they form a very low inductance and resistance cap and provide start up current for switching process?

 

[zombiess]

That was clear, but I wanted to add that another boards I have with similar inductances ring, so my conclusion is that low inductance alone is not the key to eliminate the ringing.
I think it is the added Cgs that makes a big difference if it is placed in a specific location, that's why I'm wondering where did you place it on your board?

(My layout is another story, I'll start a thread for that.)

Gotcha, we had some miscommunication.

I place my gate-source capacitance pretty much anywhere near the MOSFETs. I have not found location to play any role in my own testing. When paralleling devices I have tried one cap per MOSFET, a cap at each end of the traces and a cap right in the middle. The placement did not make any noticeable difference from what I remember, can't seem to find any notes I might have made on it several years ago, but I have a huge amount of notes on paralleling to dig through.

These are my notes on parasitics from my array of 11 paralleled TO-247 IRFP4568s I stumbled across which you might find interesting.

Measurements from apparatus #2

Natural ringing freq 10.0 MHz
Added capacitance = 0.96 uF
New ringing freq measured over 3 measurements = 0.658 MHz

Parasitics
4.2nF capacitance
61nF Inductance

Overlapped DC Bus area 18.88 in^2
0.01218 m^2

Capacitance per in^2 = 4.2/18.88=0.2225 nF
Inductance per in^2 = 61/18.88 = 3.2309 nH
Capacitance per m^2 = 4.2/0.01218=344.82759 nF
Inductance per m^2 = 61/0.01218=5,008.2 nH

I also agree that low DC bus inductance along doesn't fix it 100%, but it is key as the bus can't store much energy in the resulting magnetic field. Adding some additional G-S capacitance resolves a lot of the overshoot. I've also noticed it improves current sharing and works to slow switching time down when increasing the gate resistor doesn't provide the desired effect. With 2 paralleled devices and 10 ohm on/off resistors my natural switching frequency is <100ns on my most recent build. I found this surprisingly fast. Increasing to 20ohms made very little difference, but adding a 10nF G-S cap (measured at ~7.5nF) to one of the MOSFETs legs (I forgot to provision the PCB for a SMD resistor) provided very clean switching with very little turn off overshoot or ringing, better current sharing and D-S switching time of ~300ns. Downside is it increases power demand from the gate driver, but that is a non issue on my designs. In some of my previous G-S cap experiments I have observed that the amount needed to quell DC bus effects comes on suddenly. Adding 4.7nF to my current design made little difference, but going to 10nF made a huge improvement. Going to 15nF did not provide much additional benefit, neither did 20nF or 47nF other than slowing down the switching times.

Is your lauout with 6 lyers availbale on forum? From pictures how would you read rise time, time until reach full gate voltage or time until passes some value above treshold which provides me desired current?
Shouldn’t be surface of DC two copper plates be as big as possible because they form a very low inductance and resistance cap and provide start up current for switching process?

This is my most recent build:
https://endless-sphere.com/forums/viewtopic.php?f=30&t=106688

Inductance between two plates is a follows this relationship.
L = (u0*d*l)/w
u0 permittivity of free space
d = distance between plates
l = length of plate
w= width of plate

Good references:
http://www.nessengr.com/techdata/inductance/induc.html
http://www.pulsedpower.eu/toolbox/toolbox_inductances.html

 

[bdj]

Here are results adding 10nF across each GS. Adding 20nF did not change anything exepct longer gate times. Currently didn’t have lower values than 10nF. Power supply was 12V current same 33A. Vds peak overshoot reduced from 28V to 21V. Soon I will try with higher power supply of 50V and post.

With 10nF on high side and 47nF on low side.
Vds peak overshoot reduced to 17-18V.

 

[zombiess]

Here are results adding 10nF across each GS. Adding 20nF did not change anything exepct longer gate times. Currently didn’t have lower values than 10nF. Power supply was 12V current same 33A. Vds peak overshoot reduced from 28V to 21V. Soon I will try with higher power supply of 50V and post.
7F924926-DABE-4D13-AF34-05AE1A3A7BE6.jpeg
With 10nF on high side and 47nF on low side.
Vds peak overshoot reduced to 17-18V.
D42D01E4-7BDC-45CC-B074-4E35D5F9AA83.jpeg

10nF + 10nF in series = 5nF

Definitely try again at higher voltage. Have you tried doing a differential measurement with 2 probes to eliminate common mode noise? Some of what you are seeing might be noise from the probes. Place both the tip and ground on the same point and you should see near zero ring, but if you don't that's noise in your measurement device. Differential probes are pricey, but if you don't have access to one you can try using 2 channels on your scope to do the poor mans version.

 

[bdj]

10nF + 10nF in series = 5nF

agree

Tommorrow I will record also both Vds and Vgs from both fets. Vgs rise and fall time on lower fet extended above 1uS.
Here are results with 45Vdc and 60Vdc. And looks very good Current in both tests was 33A. Used 12V motor with stucked rotor from hand battery drill.
On both pictures time division is 50nS, on first there is 10V/div and on second 20V/div.


Concerning diff measurement with two probes, you are refering to this scenario on picture below?
I measured like understand you from probe 1 both tip and GND on S of lower fet. GND from probe 2 also on S of lower fet and tip from same probe goes to D of lower fet. Here is data recorded. Blue is D, yellow is S and purple is diff.

 

[zombiess]

My mistake, the 2 probe method worsens CMRR (ive only done this a few times myself year ago). I only use differential probes for this type of work because i got tired of noise on my measurements and not trusting them. With normal probes it's important to keep the loop super short, so you shouldn't be using the long lead most probes have, but one you can solder in place that looks like a spring.

If you hook the ground and the tip together then place them on different points like drain or source and trigger switching event, what does the scope show? Ideally it should be a flat line, anything other than that is noise in your equipment. I had several volts of noise in my own.

I'm surprised at how much ring is in your layout for the current.

 

[fechter]

I bet most of the ring is from the scope probe ground.