Some early tests.
The first tests were done with IRFP4110 (100V) FETs, with only 2 of them and the 5 big DCbus capacitors soldered on the board and some small gate driver resistors. The goal of this was to see the high frequency oscillations in the output loop (the 2 FETs and the capacitors) and estimate the loop inductance. It was a double pulse test at 70A on an inductor load that was between the output and the GND, so the high-side FET controlled the transition.
Setup:
This measurement was done with a long probe wire (~40cm) which had some boost at high frequency, and di/dt also induced voltage in the probe loop at the clips, so the amplitude on the waveforms are not exact, but the oscillations are not probe ringing. (I'll post also probe oscillations for comparison.)
These are some typical waveforms with IRFP4110, the first transition on the left is the FET turn-off at the high current, the other on the right is the turn-on.
High side Vgs, marked some points for reference that can be identified on all Vgs and Vds waveforms.
Is: source current of the FET
Irr: reverse recovery current of the other FET
Iout: output current (~70A)
Note that the measured external Vgs is the sum of the internal Vgs on the silicon chip inside the case and the voltage on the source inductance from the chip to outside the case, and ringing at the Miller-plateau of rising edge is on the source inductance (that is a part of the output loop inductance), only a small part of it can be on the chip.
High side Vds:
Low side Vds. The main oscillation appearing everywhere is on the Coss of this FET with the loop inductance after the reverse recovery of its internal diode.
The measured frequency at 60V supply voltage is 42MHz (from number of cycles in 500ns), and the Coss of IRFP4110 at 60V is ~0.6nF (from the graphs in the datasheet), so the calculated loop inductance is 23.9nH, that was better than expected with only the electrolytic capacitors.
Then I added one ceramic capacitor:
High-side Vds with ceramic capacitor:
A little less overshoot and the frequency increased to 45MHz, L reduced to 20.8nH, that is not very much difference.
At the high level a slight ~1.2MHz oscillation appeared, that is a DCbus voltage ringing between the electrolytic and the ceramic capacitors. This must be counted for at high current if there is some distance between different capacitors.
Then I tried one more pair of FETs in another channel with its legs bent at the wide part in 45degrees, because I wanted to test how much the length of the legs change the inductance. The legs are 2mm shorter.
The waveform is very similar so I don't attach, but the frequency increased to 49MHz, and the inductance was 17.6nH. There are 4 legs in an output loop, the difference is altogether 8mm -> (20.8nH-17.6nH)/8mm=0.4nH/mm
With vertically placed FETs the legs are a ~1mm even shorter, so the inductance is even lower, that matches the tests on my older design, where the inductance was 16..17nH. On that board there was no space for the snubbers, so I made the newer one.
The older board with vertical FETs:
The conclusion is that the vertical placement is significantly better than the horizontal with the legs bent in 90degrees, because the loop inductance is 4-5nH smaller, and also the gate circuit connection is closer to the chip, so the inductive voltages in the gate driver circuit are smaller.
But I wanted to follow the standard procedure, because bending the wide part of the legs is not recommended by the FET manufacturers, so I removed these FETs and changed to IRFP4568-s, because the overshoot was predictably above 100V at 90V supply voltage.
Another option for horizontal placement would be to bend the wide part of the legs in an arc with radius of 1mm, that would be advantageous for both the inductance and the cooling surface, maybe I'll try that sometime on an improved version and I would recommend that for other designs.